LAN9215I-MT SMSC, LAN9215I-MT Datasheet - Page 88
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LAN9215I-MT
Manufacturer Part Number
LAN9215I-MT
Description
Ethernet ICs Indust Hi Efficient Single-Chip
Manufacturer
SMSC
Type
Single Chip MAC and PHY Controllerr
Datasheet
1.LAN9215I-MT.pdf
(139 pages)
Specifications of LAN9215I-MT
Ethernet Connection Type
10 Base-T, 100 Base-TX
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Product
Ethernet Controllers
Number Of Transceivers
1
Standard Supported
802.3, 802.3u
Data Rate
10 Mbps, 100 Mbps
Supply Voltage (max)
5 V
Supply Voltage (min)
3.3 V
Supply Current (max)
69 mA
Maximum Operating Temperature
+ 85 C
Package / Case
TQFP-100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LAN9215I-MT
Manufacturer:
XILINX
Quantity:
450
Company:
Part Number:
LAN9215I-MT
Manufacturer:
Standard
Quantity:
6 176
Company:
Part Number:
LAN9215I-MT
Manufacturer:
SMSC32
Quantity:
51
Revision 2.7 (03-15-10)
5.3.14
30:28
26:24
22:20
18:16
15:11
BITS
10:8
7:5
31
27
23
19
Reserved
LED[3:1] enable (LEDx_EN). A ‘1’ sets the associated pin as an LED
output. When cleared low, the pin functions as a GPIO signal.
Reserved
GPIO Interrupt Polarity 0-2 (GPIO_INT_POL). When set high, a high logic
level on the corresponding GPIO pin will set the corresponding INT_STS
register bit. When cleared low, a low logic level on the corresponding GPIO
pin will set the corresponding INT_STS register bit.
GPIO Interrupts must also be enabled in GPIOx_INT_EN in the INT_EN
register.
Note:
Reserved
EEPROM Enable (EEPR_EN). The value of this field determines the
function of the external EEDIO and EECLK:
Please refer to
Note:
Note:
Reserved
GPIO Buffer Type 0-2 (GPIOBUFn). When set, the output buffer for the
corresponding GPIO signal is configured as a push/pull driver. When
cleared, the corresponding GPIO set configured as an open-drain driver.
Reserved
GPIO Direction 0-2 (GPDIRn). When set, enables the corresponding GPIO
as output. When cleared the GPIO is enabled as an input.
Reserved
LED1/GPIO0 – bit 28
LED2/GPIO1 – bit 29
LED3/GPIO2 – bit 30
GPIO0 – bit 24
GPIO1 – bit 25
GPIO2 – bit 26
GPIO0 – bit 16
GPIO1 – bit 17
GPIO2 – bit 18
GPIO0 – bit 8
GPIO1 – bit 9
GPIO2 – bit 10
GPIO_CFG—General Purpose IO Configuration Register
This register configures the GPIO and LED functions.
Offset:
GPIO inputs must be active for greater than 40nS to be recognized
as interrupt inputs.
The host must not change the function of the EEDIO and EECLK
pins when an EEPROM read or write cycle is in progress. Do not
use reserved settings.
Regardless of whether the internal or external PHY is selected,
RX_DV, TX_CLK and RX_CLK reflect the signals on the internal
PHY and the MAC always drives TX_EN.
Table 5.4
for the EEPROM Enable bit function definitions.
DESCRIPTION
88h
DATASHEET
16-bit Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support
88
Size:
32 bits
TYPE
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
RO
RO
RO
SMSC LAN9215i
DEFAULT
Datasheet
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