LAN9313I-NZW SMSC, LAN9313I-NZW Datasheet - Page 122

Ethernet ICs Three Port 10/100 Ethernet Switch

LAN9313I-NZW

Manufacturer Part Number
LAN9313I-NZW
Description
Ethernet ICs Three Port 10/100 Ethernet Switch
Manufacturer
SMSC
Type
Three Port Managed Ethernet Switchr
Datasheet

Specifications of LAN9313I-NZW

Ethernet Connection Type
10 Base-T, 100 Base-TX
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Product
Ethernet Switches
Number Of Transceivers
1
Standard Supported
802.3, 802.3u
Data Rate
10 Mbps, 100 Mbps
Supply Voltage (max)
3.3 V
Supply Voltage (min)
0 V
Supply Current (max)
155 mA, 270 mA
Maximum Operating Temperature
+ 70 C
Package / Case
TQFP-100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Revision 1.7 (06-29-10)
8.5.2
LAN9313/LAN9313i, the master may either send data bytes to be written, or it may send another start
condition (to start the reading of data), or a stop condition. The latter two will terminate the current
write (without writing any data), but will have the affect of setting the internal register address which
will be used for subsequent reads.
If the read/write indication in the control byte is a 1 (indicating a read), the LAN9313/LAN9313i will
start sending data following the control byte acknowledgement.
Note: All registers are accessed as DWORDs. Appending two 0 bits to the address field will form the
I
Following the device addressing, as detailed in
LAN9313/LAN9313i when the master sends a start condition and control byte with the R/~W bit set.
Assuming the slave address in the control byte matches the LAN9313/LAN9313i address, the control
byte is acknowledged by the LAN9313/LAN9313i. Otherwise, the entire sequence is ignored until the
next start condition. Following the acknowledge, the LAN9313/LAN9313i sends 4 bytes of data. The
first 3 bytes are acknowledged by the master and on the fourth, the master sends a no-acknowledge
followed by the stop condition. The no-acknowledge informs the LAN9313/LAN9313i not to send the
next 4 bytes (as it would in the case of a multiple read). The internal register address is unchanged
following the single read.
Multiple reads are performed when the master sends an acknowledge on the fourth byte. The internal
address is incremented and the next register is shifted out. Once the internal address reaches its
maximum, it rolls over to 0. The multiple read is concluded when the master sends a no-acknowledge
followed by a stop condition. The no-acknowledge informs the LAN9313/LAN9313i not to send the next
4 bytes. The internal register address in incremented for each read including the final.
For both single and multiple reads, in the case that the master sends a no-acknowledge on any of the
first three bytes of the register, the LAN9313/LAN9313i will stop sending subsequent bytes. If the
master sends an unexpected start or stop condition, the LAN9313/LAN9313i will stop sending
immediately and will respond to the next sequence as needed.
Since data is read serially, register values are latched (registered) at the beginning of each 32-bit read
to prevent the host from reading an intermediate value. The latching occurs multiple times in a multiple
read sequence. In addition, any register that is affected by a read operation (e.g. a clear on read bit)
is not cleared until after all 32-bits are output. In the event that 32-bits are not read (master sends a
no-acknowledge on one of the first three bytes or a start or stop condition occurs unexpectedly), the
read is considered invalid and the register is not affected. Multiple registers may be cleared in a
multiple read cycle, each one being cleared as it is read. I
return all zeros.
2
C Slave Read Sequence
register address. Addresses and data are transferred msb first. Data is transferred MSB first
(little endian).
S
S
A
6
S
A
5
Control Byte
S
A
4
S
A
3
Figure 8.3 I
S
A
2
S
A
1
S
A
0
R/~W
DATASHEET
0
2
C Slave Addressing
A
C
K
122
A
9
A
8
Address Byte
A
7
Section
A
6
A
5
2
Data [31]
C reads from unused register addresses
Start or
Stop or
Three Port 10/100 Managed Ethernet Switch with MII
A
4
8.5.1, a register is read from the
A
3
A
2
A
C
K
*
SMSC LAN9313/LAN9313i
Datasheet

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