LAN9218I-MT SMSC, LAN9218I-MT Datasheet - Page 117
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LAN9218I-MT
Manufacturer Part Number
LAN9218I-MT
Description
Ethernet ICs Indust Hi Perfrm Single-Chip
Manufacturer
SMSC
Type
Single Chip MAC and PHY Controllerr
Datasheet
1.LAN9218I-MT.pdf
(133 pages)
Specifications of LAN9218I-MT
Ethernet Connection Type
10 Base-T, 100 Base-TX
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Product
Ethernet Controllers
Number Of Transceivers
1
Standard Supported
802.3, 802.3u
Data Rate
10 Mbps, 100 Mbps
Supply Voltage (max)
3.3 V
Supply Voltage (min)
0 V
Supply Current (max)
69 mA
Maximum Operating Temperature
+ 85 C
Package / Case
TQFP-100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Part Number:
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Manufacturer:
Standard
Quantity:
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Part Number:
LAN9218I-MT
Manufacturer:
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High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support
Datasheet
SMSC LAN9218i
6.3
SYMBOL
nCS, nRD
t
t
t
t
t
t
t
t
csdv
acyc
t
csh
asu
adv
don
doff
doh
A[7:5]
A[4:1]
Data Bus
ah
In this mode, performance is improved by allowing up to 8 DWORD read cycles, or 16 WORD read
cycles back-to-back. PIO Burst Reads can be performed using Chip Select (nCS) or Read Enable
(nRD). Either or both of these control signals must go high between bursts for the period specified.
Timing for 16-bit and 32-bit PIO Burst Mode Read cycles is identical, with the exception that D[31:16]
are not driven during a 16-bit burst.
Note: The “Data Bus” width is 32 bits with optional support for 16-bit bus widths
Note: A PIO Burst Read cycle begins when both nCS and nRD are asserted. The cycle ends when
PIO Burst Reads
DESCRIPTION
nCS, nRD Deassertion Time
nCS, nRD Valid to Data Valid
Address Cycle Time
Address Setup to nCS, nRD valid
Address Stable to Data Valid
Address Hold Time
Data Buffer Turn On Time
Data Buffer Turn Off Time
Data Output Hold Time
either or both nCS and nRD are deasserted. They may be asserted and deasserted in any
order.
Figure 6.2 PIO Burst Read Cycle Timing
Table 6.4 PIO Burst Read Timing
DATASHEET
117
MIN
13
45
0
0
0
0
TYP
MAX
Revision 2.7 (03-15-10)
30
40
7
UNITS
ns
ns
ns
ns
ns
ns
ns