LAN9312-NU SMSC, LAN9312-NU Datasheet - Page 107
LAN9312-NU
Manufacturer Part Number
LAN9312-NU
Description
Ethernet ICs Hi Per 2 Port 10/100 Ethernet Switch
Manufacturer
SMSC
Type
Two Port Managed Ethernet Switchr
Datasheet
1.LAN9312-NZW.pdf
(458 pages)
Specifications of LAN9312-NU
Ethernet Connection Type
10 Base-T, 100 Base-TX
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Product
Ethernet Switches
Number Of Transceivers
1
Standard Supported
802.3, 802.3u
Data Rate
10 Mbps, 100 Mbps
Supply Voltage (max)
3.3 V
Supply Voltage (min)
0 V
Supply Current (max)
185 mA, 295 mA
Maximum Operating Temperature
+ 70 C
Package / Case
TQFP-100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LAN9312-NU
Manufacturer:
Microchip Technology
Quantity:
10 000
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High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9312
8.4.5
D[31:0] (OUTPUT)
END_SEL
nCS, nRD
A[4:2]
A[x:5]
PIO Burst Reads
In this mode, performance is improved by allowing up to 8 DWORD read cycles back-to-back. PIO
burst reads can be performed using Chip Select (nCS) or Read Enable (nRD). A PIO Burst Read
begins when both nCS and nRD are asserted. Either or both of these control signals must de-assert
between bursts for the period specified in
page
asserted and de-asserted in any order. Read data is valid as indicated in the functional timing diagram
in
Note: Fresh data is supplied each time A[2] toggles.
The endian select signal (END_SEL) has the same timing characteristics as the upper address lines.
Please refer to
specifications for PIO burst read operations.
Note: PIO burst reads are only supported for the RX Data FIFO. Burst reads from other registers are
Figure
446. The burst cycle ends when either or both nCS and nRD are de-asserted. They may be
not supported.
8.4.
Figure 8.4 Functional Timing for PIO Burst Read Operation
Section 15.5.5, "PIO Burst Read Cycle Timing," on page 446
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DATASHEET
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107
Table 15.9, “PIO Burst Read Cycle Timing Values,” on
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Revision 1.7 (06-29-10)
for the AC timing
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