LAN9312-NZW SMSC, LAN9312-NZW Datasheet
LAN9312-NZW
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LAN9312-NZW Summary of contents
Page 1
... Switch Management — Port mirroring/monitoring/sniffing: ingress and/or egress traffic on any ports or port pairs — Fully compliant statistics (MIB) gathering counters — Control registers configurable on-the-fly SMSC LAN9312 LAN9312 High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Ports — ...
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... LAN9312-NU For 128-Pin, VTQFP Lead-Free RoHS Compliant Package (0 TO 70°C Temp Range) LAN9312-NZW For 128-Pin, XVTQFP Lead-Free RoHS Compliant Package (0 TO 70°C Temp Range) This product meets the halogen maximum concentration values per IEC61249-2-21 For RoHS compliance and environmental information, please visit 80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123 Copyright © ...
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... Host MAC Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Chapter 5 System Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5.1 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5.2 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5.2.1 1588 Time Stamp Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5.2.2 Switch Fabric Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5.2.3 Ethernet PHY Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5.2.4 GPIO Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5.2.5 Host MAC Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5.2.6 Power Management Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 SMSC LAN9312 3 DATASHEET Revision 1.7 (06-29-10) ...
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... Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 7.2.1.1 MII MAC Interface ........................................................................................................................................................................................... 84 7.2.1.2 4B/5B Encoder................................................................................................................................................................................................ 84 7.2.1.3 Scrambler and PISO ....................................................................................................................................................................................... 86 7.2.1.4 NRZI and MLT-3 Encoding ............................................................................................................................................................................. 86 7.2.1.5 100M Transmit Driver ..................................................................................................................................................................................... 86 Revision 1.7 (06-29-10) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface 4 DATASHEET Datasheet SMSC LAN9312 ...
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... RX Data FIFO Direct PIO Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 8.4.7 RX Data FIFO Direct PIO Burst Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 8.4.8 PIO Writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 8.4.9 TX Data FIFO Direct PIO Writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 8.5 HBI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Chapter 9 Host MAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 9.1 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 SMSC LAN9312 5 DATASHEET Revision 1.7 (06-29-10) ...
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... WRAL (Write All)........................................................................................................................................................................................... 148 10.2.4 EEPROM Loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 10.2.4.1 EEPROM Loader Operation ......................................................................................................................................................................... 149 10.2.4.2 EEPROM Valid Flag ..................................................................................................................................................................................... 151 10.2.4.3 MAC Address................................................................................................................................................................................................ 151 Revision 1.7 (06-29-10) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface 6 DATASHEET Datasheet SMSC LAN9312 ...
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... General Purpose I/O Configuration Register (GPIO_CFG) .......................................................................................................................... 192 14.2.3.2 General Purpose I/O Data & Direction Register (GPIO_DATA_DIR) ........................................................................................................... 194 14.2.3.3 General Purpose I/O Interrupt Status and Enable Register (GPIO_INT_STS_EN)...................................................................................... 195 14.2.3.4 LED Configuration Register (LED_CFG) ...................................................................................................................................................... 196 14.2.4 EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 SMSC LAN9312 7 DATASHEET Revision 1.7 (06-29-10) ...
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... Host MAC Wake-up Control and Status Register (HMAC_WUCSR 284 14.4 Ethernet PHY Control and Status Registers 285 14.4.1 Virtual PHY Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 Revision 1.7 (06-29-10) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface 8 DATASHEET Datasheet SMSC LAN9312 ...
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... Switch Engine VLAN Command Status Register (SWE_VLAN_CMD_STS) ............................................................................................... 378 14.5.3.12 Switch Engine DIFFSERV Table Command Register (SWE_DIFFSERV_TBL_CFG)................................................................................. 379 14.5.3.13 Switch Engine DIFFSERV Table Write Data Register (SWE_DIFFSERV_TBL_WR_DATA) ...................................................................... 380 14.5.3.14 Switch Engine DIFFSERV Table Read Data Register (SWE_DIFFSERV_TBL_RD_DATA) ....................................................................... 381 SMSC LAN9312 9 DATASHEET Revision 1.7 (06-29-10) ...
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... RX Data FIFO Direct PIO Burst Read Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448 15.5.8 PIO Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449 15.5.9 TX Data FIFO Direct PIO Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 15.5.10 Microwire Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451 Revision 1.7 (06-29-10) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface 10 DATASHEET Datasheet SMSC LAN9312 ...
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... High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 15.6 Clock Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452 Chapter 16 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453 16.1 128-VTQFP Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453 16.2 128-XVTQFP Package Outline 455 Chapter 17 Datasheet Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457 SMSC LAN9312 11 DATASHEET Revision 1.7 (06-29-10) ...
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... List of Figures Figure 2.1 Internal LAN9312 Block Diagram Figure 2.2 System Block Diagram Figure 3.1 LAN9312 128-VTQFP Pin Assignments (TOP VIEW Figure 3.2 LAN9312 128-XVTQFP Pin Assignments (TOP VIEW Figure 4.1 PME and PME_INT Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Figure 5.1 Functional Interrupt Register Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Figure 6 ...
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... Figure 15.9 TX Data FIFO Direct PIO Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 Figure 15.10Microwire Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451 Figure 16.1 LAN9312 128-VTQFP Package Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453 Figure 16.2 LAN9312 128-VTQFP Recommended PCB Land Pattern 454 Figure 16.3 LAN9312 128-XVTQFP Package Definition 455 Figure 16.4 LAN9312 128-XVTQFP Recommended PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . 456 SMSC LAN9312 13 DATASHEET Revision 1 ...
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... Table 3.8 PLL Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 3.9 Core and I/O Power and Ground Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 3.10 No-Connect Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 4.1 Reset Sources and Affected LAN9312 Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 4.2 Soft-Strap Configuration Strap Definitions Table 4.3 Hard-Strap Configuration Strap Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 6.1 Switch Fabric Flow Control Enable Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Table 6 ...
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... Table 15.13TX Data FIFO Direct PIO Write Cycle Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 Table 15.14Microwire Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451 Table 15.15LAN9312Crystal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452 Table 16.1 LAN9312 128-VTQFP Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453 Table 16.2 LAN9312 128-XVTQFP Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456 Table 17.1 Customer Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457 SMSC LAN9312 15 DATASHEET ...
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... Ethernet frame, used for error detection and correction. First In First Out buffer Finite State Machine General Purpose I/O Host Bus Interface. The physical bus connecting the LAN9312 to the host. Also referred to as the Host Bus. Host Bus Interface Controller. The hardware module that interfaces the LAN9312 to the HBI. ...
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... Not Applicable No Connect Organizationally Unique Identifier Refers to data output from the LAN9312 to the host Program I/O cycle. An SRAM-like read or write cycle on the HBI. Parallel In Serial Out Phase Locked Loop Precision Time Protocol Refers to a reserved bit field or address ...
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... Note: Internal pull-up resistors prevent unconnected inputs from floating. Do not rely on internal resistors to drive signals external to the LAN9312. When connected to a load that must be pulled high, an external resistor must be added. PD 50uA (typical) internal pull-down. Unless otherwise noted in the pin description, internal pull-downs are always enabled ...
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... Many of these register bit notations can be combined. Some examples of this are shown below: R/W: Can be written. Will return current setting on a read. R/WAC: Will return current setting on a read. Writing anything clears the bit. SMSC LAN9312 Table 1.2 Register Bit Types REGISTER BIT DESCRIPTION ...
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... Ethernet and Fast Ethernet applications. At the core of the LAN9312 is the high performance, high efficiency 3 port Ethernet switch fabric. The switch fabric contains a 3 port VLAN layer 2 switch engine that supports untagged, VLAN tagged, and priority tagged frames ...
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... System Clocks/ Time Stamp Interrupt Reset/PME Clock/Events Controller Free-Run Controller Clk IRQ External 25MHz Crystal Figure 2.1 Internal LAN9312 Block Diagram Virtual PHY MII Registers Host MAC MDIO TX/RX FIFOs Host Bus Interface Register To 32-bit Access Host Bus MUX EEPROM Loader ...
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... Pin Reset A multi-module reset is initiated by assertion of the following: Digital Reset - DIGITAL_RST (bit 0) in the - Resets all LAN9312 sub-modules except the Ethernet PHYs (Port 1 PHY, Port 2 PHY, and Virtual PHY) Soft Reset - SRST (bit 0) in the - Resets the HBI, Host MAC, and System CSRs below address 100h ...
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... Ethernet PHYs The LAN9312 contains three PHYs: Port 1 PHY, Port 2 PHY and a Virtual PHY. The Port 1 & 2 PHYs are identical in functionality and each connect their corresponding Ethernet signal pins to the switch fabric MAC of their respective port. These PHYs interface with their respective MAC via an internal MII interface ...
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... Time stamping is supported on all ports, with an individual IEEE 1588 Time Stamp module connected to each port via the MII bus. Any port may function as a master or a slave clock per the IEEE 1588 specification, and the LAN9312 as a whole may function as a boundary clock. ...
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... LAN9312 system configuration and status registers. The LAN9312 utilizes the internal Host MAC to provide a network path for the host CPU. The LAN9312 may share the host bus with additional system memory and/or peripherals. For more information on the HBI, refer to page 99 ...
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... RXN2 124 VDD33A2 125 TXP2 126 TXN2 127 VSS 128 Figure 3.1 LAN9312 128-VTQFP Pin Assignments (TOP VIEW) Revision 1.7 (06-29-10) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface SMSC LAN9312 128-VTQFP TOP VIEW 26 DATASHEET Datasheet ...
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... RXP2 123 RXN2 124 VDD33A2 125 TXP2 126 TXN2 127 VSS 128 Figure 3.2 LAN9312 128-XVTQFP Pin Assignments (TOP VIEW) SMSC LAN9312 SMSC LAN9312 128-XVTQFP TOP VIEW VSS NOTE: EXPOSED PAD ON BOTTOM OF PACKAGE MUST BE CONNECTED TO GROUND 27 DATASHEET VDD33IO 64 63 IRQ ...
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... Pin Descriptions This section contains the descriptions of the LAN9312 pins. The pin descriptions have been broken into functional groups as follows: LAN Port 1 Pins LAN Port 2 Pins LAN Port 1 & 2 Power and Common Pins Host Bus Interface Pins EEPROM Pins Dedicated Configuration Strap Pins ...
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... EXRES AI Bias Reference: Used for internal bias circuits. Connect to an external 12.4K ohm, 1% resistor to ground. VDD33A1 P +3.3V Port 1 Analog Power Supply Refer to the LAN9312 application note for additional connection information. 29 DATASHEET DESCRIPTION (LED_CFG), LED Configuration Register General Purpose I/O Configuration and General Purpose I/O (GPIO_DATA_DIR) ...
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... Refer to the LAN9312 application note for additional connection information. P +1.8V Port 1 Transmitter Power Supply: This pin must be connected directly to the VDD18TX2 pin for proper operation. Refer to the LAN9312 application note for additional connection information. Table 3.4 Host Bus Interface Pins BUFFER SYMBOL TYPE ...
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... SYMBOL TYPE IS Data FIFO Direct Access Select: When driven high, all accesses to the LAN9312 are directed to the RX and TX Data FIFO’s. All reads are from the RX Data FIFO, and all writes are to the TX Data FIFO. In this mode, the address input is ignored. ...
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... EEPROM and is recommended if no EEPROM is attached. Section 2 137. This bit is not used for I C Note 3. mode (EEPROM_TYPE=1), this pin is not used and is driven low. Section 137. See Note 3.4. Section 15.5.2, "Reset and Section 15.5.2, "Reset and 2 C mode. SMSC LAN9312 Section ...
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... Note 3.6 Configuration strap values are latched on power-on reset or nRST de-assertion. Configuration strap pins are identified by an underlined symbol name. Some configuration straps can be overridden by values from the EEPROM Loader. Refer to "Configuration Straps," on page 40 SMSC LAN9312 BUFFER SYMBOL TYPE LED_EN ...
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... Register Chapter 5, "System Interrupts," on page nRST IS System Reset Input: This active low signal allows external hardware to reset the LAN9312. The (PU) LAN9312 also contains an internal power-on reset circuit. Thus, this signal may be left unconnected if an external hardware reset is not needed. When ...
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... P Digital Core +1.8V Power Supply Output: +1.8V power from the internal core voltage regulator. All VDD18CORE pins must be tied together for proper operation. Refer to the LAN9312 application note for additional connection information. VSS P Common Ground Table 3.10 No-Connect Pins ...
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... Resets The LAN9312 provides multiple hardware and software reset sources, which allow varying levels of the LAN9312 to be reset. All resets can be categorized into three reset types as described in the following sections: Chip-Level Resets —Power-On Reset (POR) —nRST Pin Reset Multi-Module Resets — ...
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... READY bit is cleared. Writes to any address are invalid until the READY bit is set. Note: The LAN9312 must be read at least once after any chip-level reset to ensure that write operations function properly. SMSC LAN9312 ...
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... Power-On Reset (POR) A power-on reset occurs whenever power is initially applied to the LAN9312 the power is removed and reapplied to the LAN9312. This event resets all circuitry within the device. Configuration straps are latched, and the EEPROM Loader is run as a result of this reset. ...
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... Reset bit in the Upon completion of the Port 2 PHY reset, the PHY2_RST and Reset bits are automatically cleared. No other modules of the LAN9312 are affected by this reset. In addition to the methods above, the Port 2 PHY is automatically reset after returning from a PHY power-down mode. This reset differs in that the PHY power-down mode reset does not reload or reset any of the PHY registers ...
Page 40
... Configuration Straps Configuration straps allow various features of the LAN9312 to be automatically configured to user defined values. Configuration straps can be organized into two main categories: hard-straps and soft- straps. Both hard-straps and soft-straps are latched upon Power-On Reset (POR) or pin reset (nRST). ...
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... Advertisement Register (PHY_AN_ADV_x) MODE[2:0] bits of the (PHY_SPECIAL_MODES_x) Refer to the respective register definition sections for additional information. SMSC LAN9312 LED Configuration Register One pin configures the default for all 8 LED/GPIOs, but 8 separate bits are loaded by the EEPROM Loader, allowing individual control over each LED/GPIO ...
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... Section Port x PHY Basic Control Port x PHY Auto- Port x PHY Special Modes Register Port 1 Backpressure Enable bit of the Port 1 Manual Flow Control Register Port 1 Full-Duplex and (MANUAL_FC_1), 42 DATASHEET Datasheet PIN / DEFAULT VALUE 1b bit in 14.4.2.1). 1b 14.4.2.1 Port 1 Full- bits in the SMSC LAN9312 ...
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... Full Duplex (bit 6) and 10BASE-T Half Duplex (bit 5) bits of the Advertisement Register (PHY_AN_ADV_x) MODE[2:0] bits of the (PHY_SPECIAL_MODES_x) Refer to the respective register definition sections for additional information. SMSC LAN9312 Port 1 Full-Duplex Manual Flow Control bit in the Port 1 Manual Flow (MANUAL_FC_1). When configured low, is set). and ...
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... Section Port x PHY Basic Control Port x PHY Auto- Port x PHY Special Modes Register Port 2 Backpressure Enable bit of the Port 2 Manual Flow Control Register Port 2 Full-Duplex and (MANUAL_FC_2), 44 DATASHEET Datasheet PIN / DEFAULT VALUE 1b bit in 14.4.2.1). 1b 14.4.2.1 Port 2 Full- bits in the SMSC LAN9312 ...
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... These straps, along with their pin assignments are also fully defined in Chapter 3, "Pin Description and Configuration," on page SMSC LAN9312 Port 2 Full-Duplex Manual Flow Control bit in the Port 2 Manual Flow (MANUAL_FC_2) ...
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... Power Management The LAN9312 Port 1 and Port 2 PHYs and the Host MAC support several power management and wakeup features. The LAN9312 can be programmed to issue an external wake signal (PME) via several methods, including wake on LAN, wake on link status change (energy detect), and magic packet wakeup. The PME signal is ideal for triggering system power-up using remote Ethernet wakeup events ...
Page 47
... IRQ interrupt output pin, as described in on page 52. Refer to Section 7.2.9.2, "PHY Energy Detect Power-Down," on page 95 operation and configuration of the PHY energy-detect power-down mode. SMSC LAN9312 WOL_EN (bit 9) of PMT_CTRL register WOL_STS (bit 5) of PMT_CTRL register ED_EN1 (bit 14) of ...
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... High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface (PMT_CTRL). Power Management Control Register (PMT_CTRL) (PMT_CTRL). 53. for additional details on these features. 48 DATASHEET Datasheet Power Host (via the WUEN bit for wake-up frames, will be set. These Power Section and Section 9.5.1, "Magic Packet SMSC LAN9312 ...
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... Chapter 5 System Interrupts 5.1 Functional Overview This chapter describes the system interrupt structure of the LAN9312. The LAN9312 provides a multi- tier programmable interrupt structure which is controlled by the System Interrupt Controller. The programmable system interrupts are generated internally by the various LAN9312 sub-modules and can be configured to generate a single external host interrupt via the IRQ interrupt output pin ...
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... SWE_IMR of SW_IPR register SWE_IPR Port [2,1,0] MAC Interrupt Registers Bits [2,1,0] (MAC_[2,1,MII]) MAC_IMR_[2,1,MII] of SW_IPR register MAC_IPR_[2,1,MII] Port 2 PHY Interrupt Registers PHY_INTERRUPT_SOURCE_2 PHY_INTERRUPT_MASK_2 Port 1 PHY Interrupt Registers PHY_INTERRUPT_SOURCE_1 PHY_INTERRUPT_MASK_1 Power Management Control Register PMT_CTRL GPIO Interrupt Register GPIO_INT_STS_EN 50 DATASHEET Datasheet SMSC LAN9312 ...
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... The following sections detail each category of interrupts and their related registers. Refer to Chapter 14, "Register Descriptions," on page 166 5.2.1 1588 Time Stamp Interrupts Multiple 1588 Time Stamp interrupt sources are provided by the LAN9312. The top-level 1588_EVNT (bit 29) of the Interrupt Status Register (INT_STS) occurred in the ...
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... GPIO Interrupts Each GPIO[11:0] of the LAN9312 is provided with its own interrupt. The top-level GPIO (bit 12) of the Interrupt Status Register (INT_STS) General Purpose I/O Interrupt Status and Enable Register Purpose I/O Interrupt Status and Enable Register (GPIO_INT_STS_EN) and status of each GPIO[11:0] interrupt. ...
Page 53
... Interrupt Status Register (INT_STS) on page 174 for additional information on bit definitions and Host MAC operation. 5.2.6 Power Management Interrupts Multiple Power Management Event interrupt sources are provided by the LAN9312. The top-level PME_INT (bit 17) of the Management interrupt event occurred in the The Power Management Control Register (PMT_CTRL) Power Management conditions ...
Page 54
... A device ready interrupt is provided in the top-level Enable Register (INT_EN). The READY interrupt (bit 30) of the indicates that the LAN9312 is ready to be accessed after a power-up or reset condition. Writing this bit in the Interrupt Status Register (INT_STS) In order for a device ready interrupt event to trigger the external IRQ interrupt pin, bit 30 of the ...
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... Functional Overview At the core of the LAN9312 is the high performance, high efficiency 3 port Ethernet switch fabric. The switch fabric contains a 3 port VLAN layer 2 switch engine that supports untagged, VLAN tagged, and priority tagged frames. The switch fabric provides an extensive feature set which includes spanning ...
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... Table 8.1, “Read After Write Timing Rules,” on page 102 56 DATASHEET Datasheet for writing sequential register Switch Fabric address range automatically set Switch Fabric address range, a sub-set of the Table 14.3, “Switch Fabric CSR to 240. are required where SMSC LAN9312 ...
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... The user should clear the AUTO_INC and AUTO_DEC bits before reading the last data to avoid an unintended read cycle. Figure 6.2 illustrates the process required to perform a switch fabric CSR read. The minimum wait periods as specified in noted. SMSC LAN9312 CSR Write Auto Increment / Decrement Idle Write ...
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... CSR_BUSY = 0 CSR_BUSY = 0 last data? Register Yes Write Command Register Read Data Register (MANUAL_FC_MII)). Table 6.1 58 DATASHEET Datasheet min wait period CSR_BUSY = 1 Read Data No Register (Port 1 Manual Flow Control Register (MANUAL_FC_2), or Port 0(Host MAC) details the switch fabric flow control SMSC LAN9312 ...
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... Advertisement Register (VPHY_AN_ADV) Base Page Ability Register "Virtual PHY Auto-Negotiation," on page 96 SMSC LAN9312 Port x PHY Auto-Negotiation Advertisement Register an d Virtual PHY egotia tio n Advertisement Register are not affected by the values of the manual flow control register. Refer to ...
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... Flow Control packet will be loaded into the pause counter. The pause function is enabled by either Auto-negotiation, or manually as discussed in Revision 1.7 (06-29-10) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface 60 DATASHEET Datasheet Section 6.2.3, SMSC LAN9312 ...
Page 61
... Total alignment errors Total bytes received from all packets Total bytes received from good packets Total packets with a symbol error Total MAC control packets SMSC LAN9312 58. Pause frames are consumed by the MAC and not sent to (MAC_RX_CFG_x). (Section 14.5.2.3, on page 324) (Section 14.5.2.4, on page (Section 14 ...
Page 62
... DATASHEET Datasheet Port x MAC Table 14.12, “Indirectly and Section 14.5.2.25 through 349) 350) 351) 352) 353) 354) 356) SMSC LAN9312 ...
Page 63
... Bit Age / Valid Static Filter Override SMSC LAN9312 (Section 14.5.2.37, on page 358) (Section 14.5.2.38, on page (Section 14.5.2.39, on page (Section 14.5.2.40, on page (Section 14.5.2.41, on page (Section 14.5.2.42, on page 363) Switch Engine ALR Write Data 0 Register and Switch Engine ALR Write Data 1 Register (SWE_ALR_WR_DAT_1) ...
Page 64
... Revision 1.7 (06-29-10) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface (SWE_PORT_INGRSS_CFG). for additional details Switch Engine ALR Command Register (SWE_ALR_WR_DAT_0), and 64 DATASHEET Datasheet Switch Engine Port (SWE_ALR_CMD_STS), Switch Switch Engine ALR Write Data 1 SMSC LAN9312 ...
Page 65
... Switch Engine ALR Command Register (SWE_ALR_CMD) Next Entry bit step 3. Note: Refer to Section 14.5.3.1, on page 366 definitions of these registers. SMSC LAN9312 with the desired MAC address and control Switch Engine ALR Command Status Register until it is cleared. Switch Engine ALR Command Register (SWE_ALR_RD_DAT_0), and Switch Engine ALR Read Data 1 Register until either are set ...
Page 66
... ALR table (since the packet would have no destinations). Revision 1.7 (06-29-10) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface is in effect effect). 66 DATASHEET Datasheet Spanning Tree Spanning Tree SMSC LAN9312 ...
Page 67
... Source Port port default table programmable Priority 3b VLAN Priority Regeneration table per port 2b ALR Priority Figure 6.4 Switch Engine Transmit Queue Selection SMSC LAN9312 ALR Static Bit 3b DA Highest Priority programmable priority Traffic Class 3b calculation table 3b 67 DATASHEET Figure 6.4, the priority may ...
Page 68
... Resolved Priority = Resolved Priority = Default Priority[Source DIFFSERV[TOS] DIFFSERV[TC] Traffic Class[Resolved Priority] Get Queue Done 68 DATASHEET Datasheet Get Queue Highest N Priority Y ALR Static Bit N VL Higher Priority Y Y Packet is Tagged N & Use Packet is Tagged N Resolved Priority = Priority Regen[VLAN Port] Priority] Queue = SMSC LAN9312 ...
Page 69
... VLAN Priority Regeneration Table Register 2 Ingress VLAN Priority Regeneration Table Register Section 14.5.3.33, on page 401 these registers. SMSC LAN9312 6.5, the default priority is based on the ingress ports priority bits in its port VID Switch Engine VLAN Write Data Register (SWE_VLAN_RD_DATA), and Section 14.5.3.8, on page 375 for detailed VLAN register descriptions ...
Page 70
... The host CPU should discard received packets from this port when in the Disabled state. Note: There is no hardware distinction between the Blocking and Disabled states. 70 DATASHEET Datasheet ... 11 0 VID for detailed VLAN (Section (Section 6.4.10, on page 75). is used to place a port into one of the Software Action SMSC LAN9312 ...
Page 71
... Ingress Flow Metering and Coloring The LAN9312 supports hardware ingress rate limiting by metering packet streams and marking packets as either Green, Yellow, or Red according to three traffic parameters: Committed Information Rate (CIR), Committed Burst Size (CBS), and Excess Burst Size (EBS). A packet is marked Green if it does not exceed the CBS, Yellow if it exceeds to CBS but not the EBS, or Red otherwise ...
Page 72
... Section 14.5.3.29, on page 397 Figure 6.7, the priority can be based on: 72 DATASHEET Datasheet Bandwidth 100 Mbps 80 Mbps 67 Mbps 57 Mbps 50 Mbps 40 Mbps 31 Mbps 20 Mbps 10 Mbps 5 Mbps 2.5 Mbps 1 Mbps 500 Kbps 250 Kbps 100 Kbps 50 Kbps for detailed register SMSC LAN9312 ...
Page 73
... The ingress flow calculation is based on the packet type and the device configuration as shown in Figure 6.8. Y Use Precedence Flow Priority = IP Precedence Figure 6.8 Switch Engine Ingress Flow Priority Calculation SMSC LAN9312 Packet is IPv 4 Packet is IP Use Precedence Use IP VLAN Enable Programmable 3b DIFFSERV Table ...
Page 74
... Broadcast Storm Control In addition to ingress rate limiting, the LAN9312 supports hardware broadcast storm control on a per port basis. This feature is enabled via the (SWE_BCST_THROT). The allowed rate per port is specified as the number of bytes multiplied by 64 allowed to be received every 1.72 mS interval. Packets that exceed this limit are dropped. Typical ...
Page 75
... VLAN. 6.4.9 Port Mirroring The LAN9312 supports port mirroring where packets received or transmitted on a port or ports can also be copied onto another “sniffer” port. Port mirroring is configured using the Multiple mirrored ports can be defined, but only one sniffer port can be defined. ...
Page 76
... High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface of Port 0 should be set. in the Host MAC should be set to 8100h and the should be set to a value other than 8100h. This configuration 76 DATASHEET Datasheet Port x MAC Receive configures the switch to Host MAC VLAN2 Tag Host MAC VLAN1 SMSC LAN9312 ...
Page 77
... When a packet is read from the memory and sent out to the corresponding port, the used buffers are released. SMSC LAN9312 Buffer Manager Drop Level Register Buffer Manager Broadcast Buffer Level Register Section 6.4.6, " ...
Page 78
... Mbps 80 Mbps 65 Mbps 67 Mbps 56 Mbps 57 Mbps 49 Mbps 50 Mbps 39 Mbps 40 Mbps 30 Mbps 31 Mbps 20 Mbps 20 Mbps 10 Mbps 10 Mbps 5 Mbps 5 Mbps 2.5 Mbps 2.5 Mbps 990 Kbps 1 Mbps 490 Kbps 500 Kbps 250 Kbps 250 Kbps 98 Kbps 100 Kbps 49 Kbps 50 Kbps SMSC LAN9312 ...
Page 79
... Priority field of the new VLAN is changed to the egress ports default priority. When a packet is received special-tagged from a CPU port, the special tag is removed. SMSC LAN9312 Section 6.4.10, "Host CPU Port Special Tagging," on page Buffer Manager Egress Port Type Register must be set ...
Page 80
... VID = Default VID VID = Default VID [ingress_port] [ingress_port] Priority = Default Priority Priority = Unchanged [ingress_port Change Priority Y N [egress_port] Modify Tag VID = Unchanged Priority = Default Priority Send Packet Untouched [egress_port] 80 DATASHEET Datasheet Special Tagged Strip Tag Strip Tag Strip Tag SMSC LAN9312 ...
Page 81
... Buffer Manager Port 2 Ingress Rate Drop Count Register (BM_RATE_DRP_CNT_SRC_2) 6.6 Switch Fabric Interrupts The switch fabric is capable of generating multiple maskable interrupts from the buffer manager, switch engine, and MACs. These interrupts are detailed in page 51. SMSC LAN9312 Section 5.2.2, "Switch Fabric Interrupts," DATASHEET Revision 1.7 (06-29-10) ...
Page 82
... Functional Overview The LAN9312 contains three PHYs: Port 1 PHY, Port 2 PHY and a Virtual PHY. The Port 1 & 2 PHYs are identical in functionality and each connect their corresponding Ethernet signal pins to the switch fabric MAC of their respective port. These PHYs interface with their respective MAC via an internal MII interface ...
Page 83
... MII MII To Port x MAC Switch Fabric MAC Interface PHY Management MDIO Control To Host MAC Registers Interrupts To System Interrupt Controller SMSC LAN9312 and 100BASE-TX Receive and 10BASE-T Receive 10/100 Transmitter HP Auto-MDIX 10/100 Reciever LEDs To GPIO/LED Controller Figure 7.1 Port x PHY Block Diagram ...
Page 84
... Shaded blocks are those which are 100M PLL MII MAC 4B/5B 25MHz Interface by 4 bits Encoder 125 Mbps Serial 100M MLT-3 MLT-3 TX Driver MLT-3 CAT-5 Section 7.2.7, "MII MAC 84 DATASHEET Datasheet Scrambler 25MHz by 5 bits and PISO Magnetics Interface". Table 7.2. Each 4-bit data-nibble SMSC LAN9312 ...
Page 85
... MII Receive Data Valid (RXDV) 00000 /V/ INVALID, MII Receive Error (RXER) if during MII Receive Data Valid (RXDV) 00001 /V/ INVALID, MII Receive Error (RXER) if during MII Receive Data Valid (RXDV) SMSC LAN9312 Table 7.2 4B/5B Code Table RECEIVER INTERPRETATION 0000 DATA 0001 0010 0011 ...
Page 86
... MHz logic and the 100BASE-TX Transmitter. Revision 1.7 (06-29-10) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Table 7.2 4B/5B Code Table (continued) RECEIVER INTERPRETATION 86 DATASHEET Datasheet TRANSMITTER INTERPRETATION INVALID INVALID INVALID INVALID INVALID INVALID Section 7.1.1, "PHY SMSC LAN9312 ...
Page 87
... The 100M PLL generates multiple phases of the 125MHz clock. A multiplexer, controlled by the timing unit of the DSP, selects the optimum phase for sampling the data. This is used as the received recovered clock. This clock is used to extract the serial data from the received signal. SMSC LAN9312 Figure 7.3. Shaded blocks are those which are internal ...
Page 88
... Note: The PHY is connected to the switch fabric MAC via standard MII signals. Refer to the IEEE 802.3 specification for additional details. Revision 1.7 (06-29-10) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface 88 DATASHEET Datasheet Section 7.2.7, "MII MAC SMSC LAN9312 ...
Page 89
... The polarity of the signal is also checked. If the polarity is reversed (local RXP is connected to RXN of the remote partner and vice versa), then this is identified and corrected. The reversed condition is indicated by the flag “XPOL“, bit 4 in SMSC LAN9312 Section 7.2.7, "MII MAC Port x PHY Special Control/Status Indication Register ...
Page 90
... Besides the connection speed, the PHY can advertise remote fault indication and symmetric or asymmetric pause flow control as defined in the IEEE 802.3 specification. The LAN9312 does not support “Next Page” capability. Many of the default advertised capabilities of the PHY are determined via configuration straps as shown in Negotiation Advertisement Register (PHY_AN_ADV_x)," ...
Page 91
... Advertisement Register (PHY_AN_ADV_x) x PHY Basic Control Register will be advertised. Auto-negotiation can also be disabled via software by clearing bit 12 of the PHY Basic Control Register SMSC LAN9312 Reset Control Register (RESET_CTL), or bit 15 of the (Section 7.2.9, "PHY Power-Down Modes," on page Port x PHY Basic Status Register (PHY_BASIC_STATUS_x) ...
Page 92
... Parallel Detection If the LAN9312 is connected to a device lacking the ability to auto-negotiate (i.e. no FLPs are detected able to determine the speed of the link based on either 100M MLT-3 symbols or 10M Normal Link Pulses. In this case the link is presumed to be half-duplex per the IEEE 802.3 standard. ...
Page 93
... The MII MAC Interface is responsible for the transmission and reception of the Ethernet data to and from the switch fabric MAC. The PHY is connected internally to the switch fabric MAC via standard MII signals per IEEE 802.3. SMSC LAN9312 Figure 7.4 (PHY_SPECIAL_CONTROL_STAT_IND_x). When AMDIXCTRL is Section 3.2, " ...
Page 94
... System Interrupt Controller and is reflected via the the Port 1 PHY, and bit 27 (PHY_INT2) for the Port 2 PHY. For more information on the LAN9312 interrupts, refer to Chapter 5, "System Interrupts," on page ...
Page 95
... The energy detect power down feature is part of the broader power management features of the LAN9312 and can be used to trigger the power management event output pin (PME). This is accomplished by enabling the energy detect power-down feature of the PHY as described above, and setting the corresponding energy detect enable (bit 14 for Port 1 PHY, bit 15 for Port 2 PHY) of the ...
Page 96
... Host MAC was attached to a single port PHY. This functionality is designed to allow easy and quick integration of the LAN9312 into designs with minimal driver modifications. The Virtual PHY provides a full bank of registers which comply with the IEEE 802 ...
Page 97
... Auto-negotiation can be disabled in the Virtual PHY by clearing bit 12 (VPHY_AN) of the Basic Control Register to reflect the speed (bit 13) and duplex (bit 8) of the (VPHY_BASIC_CTRL). The speed and duplex bits in the (VPHY_BASIC_CTRL) SMSC LAN9312 Virtual PHY Auto-Negotiation Expansion Register Parallel Detection is used. are set to indicate the emulated link partners abilities. ...
Page 98
... Virtual PHY Resets In addition to the chip-level hardware reset (nRST) and Power-On Reset (POR), the Virtual PHY supports three block specific resets. These are is discussed in the following sections. For detailed information on all LAN9312 resets, refer to 7.3.2.1 Virtual PHY Software Reset via RESET_CTL The Virtual PHY can be reset via the (VPHY_RST) ...
Page 99
... System CSR’s: The HBI allows for configuration and monitoring of the various LAN9312 functions through the System Control and Status Registers (CSRs). These registers are accessible to the host via the Host Bus Interface and allow direct (and indirect) access to all the LAN9312 functions. For a full list of all System CSR’s and their descriptions, refer to Registers" ...
Page 100
... High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface 32-BIT LITTLE ENDIAN (END_SEL = 0) INTERNAL ORDER MSB HOST DATA BUS Figure 8.1 Little Endian Byte Ordering 32-BIT BIG ENDIAN (END_SEL = 1) INTERNAL ORDER MSB HOST DATA BUS Figure 8.2 Big Endian Byte Ordering 100 DATASHEET Datasheet LSB LSB SMSC LAN9312 ...
Page 101
... In order to prevent the host from reading stale data after a write operation, minimum wait periods have been established. These periods are specified in specified period of time after any write to the LAN9312 before reading the resource specified in the table. These wait periods are for read operations that immediately follow any write cycle. Note that the required wait period is dependant upon the register being read after the write. Performing “ ...
Page 102
... High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Table 8.1 Read After Write Timing Rules MINIMUM WAIT TIME FOR READ FOLLOWING ANY WRITE CYCLE (IN NS 135 135 315 45 135 180 102 DATASHEET Datasheet NUMBER OF BYTE_TEST READS (ASSUMING T OF 45NS) CYC SMSC LAN9312 ...
Page 103
... SMSC LAN9312 MINIMUM WAIT TIME FOR READ FOLLOWING ANY WRITE CYCLE (IN NS) (ASSUMING ...
Page 104
... SWITCH_MAC_ADDRL RESET_CTL SWITCH_CSR_DIRECT_DATA Revision 1.7 (06-29-10) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface MINIMUM WAIT TIME FOR READ FOLLOWING ANY WRITE CYCLE (IN NS 104 DATASHEET Datasheet NUMBER OF BYTE_TEST READS (ASSUMING T OF 45NS) CYC SMSC LAN9312 ...
Page 105
... There are also restrictions on specific back-to-back host read operations. These restrictions concern reading specific registers after reading a resource that has side effects. In many cases there is a delay between reading the LAN9312, and the subsequent indication of the expected change in the control and status register values. ...
Page 106
... High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Table 15.8, “PIO Read Cycle Timing Values,” on page for information on these restrictions. VALID VALID 106 DATASHEET Datasheet 445. The cycle ends when Figure 8.3. for the AC timing specifications VALID SMSC LAN9312 ...
Page 107
... Note: PIO burst reads are only supported for the RX Data FIFO. Burst reads from other registers are not supported. END_SEL A[x:5] A[4:2] nCS, nRD D[31:0] (OUTPUT) Figure 8.4 Functional Timing for PIO Burst Read Operation SMSC LAN9312 Table 15.9, “PIO Burst Read Cycle Timing Values,” on VALID VALID VALID VALID VALID VALID ...
Page 108
... RX Data FIFO Direct PIO Reads In this mode only A[2] is decoded, and any read of the LAN9312 will read the RX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a read access. This is normally accomplished by connecting the FIFO_SEL signal to a high-order address line. This mode is useful when the host processor must increment its address when accessing the LAN9312 ...
Page 109
... RX Data FIFO Direct PIO Burst Reads In this mode only A[2] is decoded, and any burst read of the LAN9312 will read the RX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a read access. This is normally accomplished by connecting the FIFO_SEL signal to a high-order address line. This mode is useful when the host processor must increment its address when accessing the LAN9312 ...
Page 110
... PIO Writes PIO writes are used for all LAN9312 write cycles. PIO writes can be performed using Chip Select (nCS) or Write Enable (nWR). A PIO write cycle begins when both nCS and nWR are asserted. The cycle ends when either or both nCS and nWR are de-asserted. Either or both of these control signals must ...
Page 111
... TX Data FIFO Direct PIO Writes In this mode only A[2] is decoded, and any write to the LAN9312 will write the TX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a write access. This is normally accomplished by connecting the FIFO_SEL signal to a high-order address line. This mode is useful when the host processor must increment its address when accessing the LAN9312 ...
Page 112
... High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface system registers. Configuration". This depth of buffer storage minimizes or Host MAC MII Access Register (HMAC_MII_ACC) (HMAC_MII_DATA). The Host MAC interfaces to the Switch Engine Port 0 via 112 DATASHEET Datasheet and Host MAC register to the ranges described in and Host SMSC LAN9312 ...
Page 113
... VLAN tag identify the tag, and by convention are set to the value 0x8100. The last two bytes identify the specific VLAN associated with the packet and provide a priority field. The LAN9312 supports VLAN-tagged packets and provides two Host MAC registers, Tag Register (HMAC_VLAN1) to identify VLAN-tagged packets ...
Page 114
... Figure 9.1 VLAN Frame (HMAC_CR), as shown in 114 DATASHEET Datasheet FCS 4 Bytes Data FCS 46-1500 Bytes 4 Bytes VLAN ID 12 Bits Defines the VLAN to which the frame belongs Canonical Address Format Indicator Table 9.1. Please refer to the Section for more information on this register. SMSC LAN9312 ...
Page 115
... However, if the incoming frame is a multicast frame, the Host MAC packet filter function performs an imperfect address filtering against the hash table. The imperfect filtering against the hash table is the same imperfect filtering process described in Section 9.4.2, "Hash Only SMSC LAN9312 Table 9.1 Address Filtering Modes HO HPFILT ...
Page 116
... Host MAC Wake-up Control and Status Register (HMAC_WUFF). The wake-up frame filter Host MAC Wake-up Frame Filter Register (HMAC_WUCSR), a broadcast wake-up frame will wake-up the device 116 DATASHEET Datasheet Host MAC (HMAC_ADDRL)) is set, all (HMAC_WUFF). Table 9.2 Host MAC Wake-up Control Host MAC Control SMSC LAN9312 ...
Page 117
... When bit is cleared, the pattern applies only to unicast frames. 2:1 RESERVED 0 Enable Filter: When bit is set, Filter i is enabled, otherwise, Filter i is disabled. SMSC LAN9312 Filter 0 Byte Mask Filter 1 Byte Mask Filter 2 Byte Mask Filter 3 Byte Mask ...
Page 118
... Host MAC examines received data for a Magic Packet. The LAN9312 can be programmed to notify the host of the “Magic Packet” detection with the assertion of the host interrupt (IRQ) or power management event signal (PME). Upon detection, the Magic Packet Received bit (MPR) in the HMAC_WUCSR register is set ...
Page 119
... For example, if the desired Ethernet physical address is 12-34-56-78-9A-BC, the HMAC_ADDRL and HMAC_ADDRH registers would be programmed as shown in automatically load this configuration from the EEPROM are also shown. SMSC LAN9312 Host MAC Address Low Register (HMAC_ADDRL) (HMAC_ADDRH). These registers contain the 48-bit physical ...
Page 120
... For more information on the EEPROM and EEPROM Loader, refer to Master EEPROM Controller," on page 9.7 FIFOs The LAN9312 contains four host-accessible FIFOs (TX Status, RX Status, TX Data, and RX Data) and two internal inaccessible Host MAC TX/RX MIL FIFO’s (TX MIL FIFO, RX MIL FIFO). 9.7.1 TX/RX FIFOs The TX/RX Data and Status FIFOs store the incoming and outgoing address and data information, acting as a conduit between the host bus interface (HBI) and the Host MAC ...
Page 121
... Note: The RX Data FIFO is considered full 4 DWORDs before the length that is specified in the HW_CFG register. FIFO TX Status RX Status TX Data RX Data SMSC LAN9312 is incremented. Hardware Configuration Register TX FIFO Size (TX_FIF_SZ) (HW_CFG). The TX_FIF_SZ field selects the total allocation for the TX data Table 9.8 TX/RX FIFO Configurable Sizes SIZE RANGE ...
Page 122
... Data is queued for transmission by writing it into the TX Data FIFO. Each packet to be transmitted may be divided among multiple buffers. Each buffer starts with a two DWORD TX command (TX command ‘A’ and TX command ‘B’). The TX command instructs the LAN9312 on the handling of the associated buffer. Packet boundaries are delineated using control bits within the TX command. ...
Page 123
... Buffer End Alignment field specified in each TX command. The host can instruct the LAN9312 to issue an interrupt when the buffer has been fully loaded into the TX FIFO contained in the LAN9312 and transmitted. This feature is enabled through the TX command ‘ ...
Page 124
... The buffer format is illustrated in Host Write Figure 9.4 shows the TX Buffer written into the LAN9312. It should be noted that not all of the data shown in this diagram is actually stored in the TX Data FIFO. This must be taken into account when calculating the actual TX Data FIFO usage. Please refer to Data FIFO Usage" ...
Page 125
... This value, along with the Buffer End Alignment field, is read and checked by the LAN9312 and used to determine how many extra DWORDs were added to the end of the Buffer. A running count is also maintained in the LAN9312 of the cumulative buffer sizes for a given packet. ...
Page 126
... High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Table 9.11 TX Command 'B' Format DESCRIPTION Table 9.12, "TX DATA Start Table 9.12 TX DATA Start Offset 11 10 D[31:24] D[23:16] 126 DATASHEET Datasheet Offset", shows the 01 00 D[15:8] D[7:0] SMSC LAN9312 ...
Page 127
... DWORDs (2,036 bytes total). Any transmit packet that is so highly fragmented that it takes more space than this must be un-fragmented (by copying to a driver-supplied buffer) before the transmit packet can be sent to the LAN9312. One approach to determine whether a packet is too fragmented is to calculate the actual amount of space that it will consume, and check it against 2,036 bytes ...
Page 128
... Start Offset” 15-Bytes of payload data 16-Byte “Buffer End Alignment” Buffer 2: 10-Byte “Data Start Offset” 17-Bytes of payload data Revision 1.7 (06-29-10) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface DESCRIPTION 128 DATASHEET Datasheet SMSC LAN9312 ...
Page 129
... TX Command 'A' Buffer End Alignment = 1 Data Start Offset = 10 First Segment = 0 Last Segment = 1 Buffer Size = 17 TX Command 'B' Packet Length = 111 SMSC LAN9312 Data Written to the Memory Mapped TX Data FIFO Port 0 TX Command 'A' TX Command 'B' 7-Byte Data Start Offset 79-Byte Payload Pad DWORD 1 ...
Page 130
... High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Memory Mapped 0 TX Command 'A' TX Command 'B' 183-Byte Payload Data 3B End Padding Figure 9.6 TX Example 2 130 DATASHEET Datasheet Data Passed to the TX Data FIFO TX Command 'A' TX Command 'B' 183-Byte Payload Data NOTE: Extra bytes between buffers are not transmitted SMSC LAN9312 ...
Page 131
... Once stopped, the host can optionally clear the TX Status and TX Data FIFOs. The host must re- enable the transmitter by setting the TX_ON bit. If the there are frames pending in the TX Data FIFO (i.e., TX Data FIFO was not purged), the transmission will resume with this data. SMSC LAN9312 Transmit Configuration Register Interrupt Status Register ...
Page 132
... The host can set an offset from 0-31 bytes. The offset may be changed in between RX packets, but it must not be changed during an RX packet read. The LAN9312 can be programmed to add padding at the end of a receive packet in the event that the end of the packet does not align with the host burst boundary. This feature is necessary when the LAN9312 is operating in a system that always performs multi-DWORD bursts ...
Page 133
... High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Last Packet Figure 9.7 Host Receive Routine Using Interrupts Last Packet Figure 9.8 Host Receive Routine Using Polling SMSC LAN9312 init Idle RX Interrupt Read RX Status DWORD Not Last Packet ...
Page 134
... The RX data path implements an automatic data discard function. Using the RX Data FIFO Fast Forward bit (RX_FFWD) in the instruct the LAN9312 to skip the packet at the head of the RX Data FIFO. The RX Data FIFO pointers are automatically incremented to the beginning of the next RX packet. When performing a fast-forward, there must be at least 4 DWORDs of data in the RX Data FIFO for the packet being discarded ...
Page 135
... Host MAC Control Register (HMAC_CR) 10 Multicast Frame. When set, this bit indicates that the received frame has a Multicast address. 9:8 Reserved. These bits are reserved. Reads 0. SMSC LAN9312 Figure 9. assumed that the host has previously read the associated Host Read 31 Order ...
Page 136
... It is the duty of the host to identify and resolve any error conditions. Revision 1.7 (06-29-10) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface DESCRIPTION Host MAC Control Register Interrupt Status Register (INT_STS) 136 DATASHEET Datasheet (HMAC_CR). Interrupt Status for any reason, SMSC LAN9312 ...
Page 137
... Various commands are supported for each EEPROM type, allowing for the storage and retrieval of static data. The I The EEPROM Loader provides the automatic loading of configuration settings from the EEPROM into the LAN9312 at reset. The EEPROM Loader module interfaces to the EEPROM Controller, Ethernet PHYs, and the system CSRs ...
Page 138
... Note: The EEPROM device powers-up in the erase/write disabled state. To modify the contents of the EEPROM, the EWEN command must first be issued operation is attempted and the EEPROM device does not respond within 30mS, the LAN9312 will time-out, and the EPC_TIMEOUT bit of the Revision 1.7 (06-29-10) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface (E2P_DATA) ...
Page 139
... Based on the configuration strap eeprom_size_strap, various sized I varying size ranges are supported by additional bits in the address field (EPC_ADDRESS) of the EEPROM Command Register address bits, while the smaller EEPROMs treat the upper address bits as don’t cares. The EEPROM SMSC LAN9312 Idle Write Register ...
Page 140
... C operation are shown in Table 2 Table 10 EEPROM Size Ranges EEPROM SIZE (Note 10. through 2048 4096 x 8 through 65536 140 DATASHEET Datasheet 10.2. EEPROM TYPES 24xx00, 24xx01, 24xx02, 24xx04, 24xx08, 24xx16 24xx32, 24xx64, 24xx128, 24xx256, 24xx512 C-Bus Specification for detailed timing SMSC LAN9312 ...
Page 141
... Address Byte Chip / Block R/~W Select Bits Single Byte Addressing SMSC LAN9312 2 C cycle. data data data can can stable change change Sr Data Valid Re-Start or Ack Condition 2 Figure 10 Cycle is set EEPROM addressing bit order for single and double byte addressing. Control Byte ...
Page 142
... Double Byte Addressing Sequential Reads 2 C EEPROM Sequential Byte Reads 142 DATASHEET Datasheet 2 is set. The I C master then Data Byte R/~W Double Byte Addressing Read Section 10.2.1, "EEPROM Controller 2 is set. The I C master then Data Byte ... Data Byte ... SMSC LAN9312 ...
Page 143
... For a register level description of a write operation, refer to Operation," on page 138. SMSC LAN9312 is set master will poll the EEPROM to determine when the byte 2 C EEPROM byte write. Poll Cycle Poll Cycle Control Byte Chip / Block R/~W Chip / Block Select Bits ...
Page 144
... Section 14.2.4.1, "EEPROM Command Register (E2P_CMD)," on ADDRESS ADDRESS 144 DATASHEET Datasheet EEPROM TYPES 93xx46A 93xx56A, 93xx66A 93xx76A, 93xx86A DATA TO DATA FROM # OF EEPROM EEPROM CLOCKS - (RDY/~BSY (RDY/~BSY Hi Hi (RDY/~BSY (RDY/~BSY) 18 DATA TO DATA FROM # OF EEPROM EEPROM CLOCKS - (RDY/~BSY (RDY/~BSY) 12 SMSC LAN9312 ...
Page 145
... ERASE (Erase Location) If erase/write operations are enabled in the EEPROM, this command will erase the location selected by the EPC_ADDRESS field of the bit is set if the EEPROM does not respond within 30mS. EECS EECLK EEDO 1 1 EEDI SMSC LAN9312 ADDRESS ADDRESS A10 A10 ...
Page 146
... EECS EECLK EEDO 1 EEDI Revision 1.7 (06-29-10) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface EEPROM Command Register (E2P_CMD Figure 10.8 EEPROM ERAL Cycle Figure 10.9 EEPROM EWDS Cycle 146 DATASHEET Datasheet is set if the SMSC LAN9312 ...
Page 147
... This command will cause a read of the EEPROM location pointed to by the EPC_ADDRESS field of the EEPROM Command Register Register (E2P_DATA). EECS EECLK EEDO 1 1 EEDI SMSC LAN9312 Figure 10.10 EEPROM EWEN Cycle (E2P_CMD). The result of the read is available in the Figure 10.11 EEPROM READ Cycle ...
Page 148
... The EPC_TIMEOUT bit of the is set if the EEPROM does not respond within 30mS Figure 10.12 EEPROM WRITE Cycle to be written to every EEPROM memory location. The EEPROM Command Register (E2P_CMD Figure 10.13 EEPROM WRAL Cycle 148 DATASHEET Datasheet D0 is set if the EEPROM does not D0 SMSC LAN9312 ...
Page 149
... EPC_BUSY bit in the While the EEPROM Loader is active, the READY bit of the (HW_CFG) and Power Management Control Register (PMT_CTRL) LAN9312 should be attempted. The operational flow of the EEPROM Loader can be seen in Figure 10.14. SMSC LAN9312 2 C/Microwire EEPROM controller, the PHYs, and to the system ...
Page 150
... High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Load PHY registers with N current straps Y Load PHY registers with N current straps Y Write Bytes 1-6 into Host MAC Address Registers N Y 150 DATASHEET Datasheet EPC_BUSY = 0 N Soft Reset Y EPC_BUSY = 1 Read Byte 0 N Byte 0 = A5h Y Read Bytes 1-6 SMSC LAN9312 ...
Page 151
... The EEPROM bytes are written into the MAC Table 10.7. Refer to (HW_CFG)), the EEPROM Loader will read byte 0. If the byte Table 10.8. If the flag byte is not A5h, these next 4 bytes are skipped Section for more information on the LAN9312 configuration straps. Table 10.8 EEPROM Configuration Bits manual_ manual_mdix ...
Page 152
... Register Data Optionally following the configuration strap values, the EEPROM data may be formatted to allow access to the LAN9312 parallel, directly writable registers. Access to indirectly accessible registers (e.g. Switch Engine registers, etc.) is achievable with an appropriate sequence of writes (at the cost of EEPROM space). This data is first preceded with a Burst Sequence Valid Flag (EEPROM byte 12). If this byte has a value of A5h, the data that follows is recognized as a sequence of bursts ...
Page 153
... In order to allow the EEPROM Loader to change the Port 1/2 PHYs and Virtual PHY strap inputs and maintain consistency with the PHY and Virtual PHY registers, the following sequence is used: 1. After power-up or upon a hardware reset (nRST), the straps are sampled into the LAN9312 as specified in Section 15.5.2, " ...
Page 154
... MII bus. Any port may function as a master or a slave clock per the IEEE 1588 specification, and the LAN9312 as a whole may function as a boundary clock. A 64-bit tunable clock is provided that is used as the time source for all IEEE 1588 time stamp related functions ...
Page 155
... High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 11.1.2 Block Diagram The LAN9312 IEEE 1588 implementation is illustrated in major function blocks: IEEE 1588 Time Stamp These three identical blocks provide time stamping functions on all switch fabric ports. ...
Page 156
... PHY. This is consistent with the point-of-view of where the partner clock resides (LAN9312 receives packets from the partner via the PHY, etc.). For the time stamp module connected to the Host MAC (Port 0), the definition of transmit and receive is reversed. Receive is defined as data from the switch fabric, while transmit is defined as data to the switch fabric ...
Page 157
... Interrupt Status and Enable Register (1588_INT_STS_EN) 14.2.5.22, "1588 Configuration Register (1588_CONFIG)," on page 222 the capture locking related bits. SMSC LAN9312 Table 11.2 details the time stamp capture delay as a function of the Chapter 7, "Ethernet PHYs," on page 82 Table 11.2 Time Stamp Capture Delay Table 11 ...
Page 158
... PTP Message Detection In order to provide the most flexibility, loose packet type matching is used by the LAN9312. This assumes that for all packets received with a valid FCS, only the MAC destination address is required to qualify them as a PTP message. For Ethernet, four multicast addresses are specified in the PTP protocol: 224 ...
Page 159
... Datasheet 11.3 IEEE 1588 Clock The 64-bit IEEE 1588 clock is the time source for all IEEE 1588 related functions of the LAN9312 readable and writable by the host via the 1588 Clock Low-DWORD Register In order to accurately read this clock, a special procedure must be followed. Since two DWORD reads are required to fully read the 64-bit clock, the possibility exists that as the lower 32-bits roll over, a wrong intermediate value could be read ...
Page 160
... GPIO[9:8] for IEEE 1588 time Section 14.2.5.23, "1588 Interrupt Status and Enable Register for bit-level definitions of all IEEE 1588 interrupts and enables. Interrupt Status Register 1588 Interrupt Status and Enable Register (1588_INT_STS_EN) Section 13.2.2, "GPIO Interrupts," on for additional information on the LAN9312 160 DATASHEET Datasheet ...
Page 161
... This chapter details the LAN9312 General Purpose Timer (GPT) and the Free-Running Clock. 12.1 General Purpose Timer The LAN9312 provides a 16-bit programmable General Purpose Timer that can be used to generate periodic system interrupts. The resolution of this timer is 100uS. The GPT loads the ...
Page 162
... General Purpose I/O Data & Direction Register (GPIO_CFG). 162 DATASHEET Datasheet Section General Purpose I/O Interrupt for additional information. General Purpose I/O Configuration (GPIO_DATA_DIR). The (GPIO_DATA_DIR). When General Purpose I/O Data & (GPIO_DATA_DIR). For GPIOs General and the 1588_GPIO_OE[9:8] bits in SMSC LAN9312 ...
Page 163
... General Purpose I/O Configuration Register 13.2.2 GPIO Interrupts Each GPIO of the LAN9312 provides the ability to trigger a unique GPIO interrupt in the Purpose I/O Interrupt Status and Enable Register bits of this register provides the current status of the corresponding interrupt, and each interrupt is enabled by setting the corresponding GPIO_INT_EN[11:0] bit. The GPIO/LED Controller aggregates ...
Page 164
... LED Configuration Register Table 13.1 followed by a detailed LED Configuration Register and its related straps, refer to 196. 10b 11b Activity - Port 2 Link - Port 2 TXEN Port 2 Port 2 Speed RXDV Port 2 Port 2 Activity TXEN Port 1 Port 0 Link RXDV Port 1 Port 0 SMSC LAN9312 LED ...
Page 165
... TXEN Port 0 - Non-stretched TXEN signal from the switch fabric to the Host MAC. RXDV Port 0 - Non-stretched RXDV signal from the Host MAC to the switch fabric. TXEN - Non-stretched TXEN signal from the switch fabric to the PHY. RXDV - Non-stretched RXDV signal from the PHY to the switch fabric. SMSC LAN9312 LED_CFG[9:8] (LED_FUN[1:0]) Full-duplex / Collision Full-duplex / Collision ...
Page 166
... Section 14.5, "Switch Fabric Control and Status Registers," on page 307 Figure 14.1 contains an overall base register memory map of the LAN9312. This memory map is not drawn to scale, and should be used for general reference only. Note: Register bit type definitions are provided in Note: Not all LAN9312 registers are memory mapped or directly addressable ...
Page 167
... Direct FIFO Access Mode When the FIFO_SEL pin is driven high, the LAN9312 enters the direct FIFO access mode. In this mode, all host write operations are to the TX Data FIFO and all host read operations are from the RX Data FIFO. When FIFO_SEL is asserted, only the A[2] host address signal is decoded. All other address signals are ignored in this mode. When the endianess select pin (END_SEL) is low, the TX/RX Data FIFO’ ...
Page 168
... General Purpose Timer Count Register, Reserved for Future Use 168 DATASHEET Datasheet Section 14.2.9.1 Section 14.2.1.1 Section 14.2.1.2 Section 14.2.1.3 Section 14.2.9.2 Section 14.2.1.4 Section 14.2.2.1 Section 14.2.2.2 Section 14.2.9.3 Section 14.2.2.3 Register,Section 14.2.2.4 Section 14.2.2.5 Section 14.2.9.4 Section 14.2.9.6 SMSC LAN9312 ...
Page 169
... SMSC LAN9312 REGISTER NAME Free Running Counter Register, Host MAC RX Dropped Frames Counter Register, Section 14.2.2.6 Host MAC CSR Interface Command Register, Section 14.2.2.7 PHY Management Interface Data Register (EEPROM Loader Access Only), Section 14 ...
Page 170
... Section 14.2.5.20 1588 Auxiliary MAC Address Low-DWORD Register, Section 14.2.5.21 1588 Configuration Register, 1588 Interrupt Status Enable Register, 1588 Command Register, 170 DATASHEET Datasheet Section 14.2.5.3 Section 14.2.5.7 Section 14.2.5.13 Section 14.2.5.14 Section 14.2.5.15 Section 14.2.5.22 Section 14.2.5.23 Section 14.2.5.24 SMSC LAN9312 ...
Page 171
... RESET_CTL 1FCh RESERVED 200h-2DCh SWITCH_CSR_DIRECT_DATA 2E0h-3FFh RESERVED SMSC LAN9312 REGISTER NAME Port 1 Manual Flow Control Register, Port 2 Manual Flow Control Register, Port 0 Flow Control Register, Switch Fabric CSR Interface Data Register, Section 14.2.6.4 Switch Fabric CSR Interface Command Register, Section 14.2.6.5 ...
Page 172
... Interrupts This section details the interrupt related System CSR’s. These registers control, configure, and monitor the IRQ interrupt output pin and the various LAN9312 interrupt sources. For more information on the LAN9312 interrupts, refer to 14.2.1.1 Interrupt Configuration Register (IRQ_CFG) Offset: This read/write register configures and indicates the state of the IRQ signal ...
Page 173
... IRQ pin open-drain output 1: IRQ pin push-pull driver Note 14.1 Register bits designated as NASR are not reset when either the SRST bit in the Configuration Register (HW_CFG) Register (RESET_CTL) SMSC LAN9312 DESCRIPTION register or the DIGITAL_RST bit in the is set. 173 DATASHEET ...
Page 174
... Register (INT_EN) is set high. Writing a one clears this interrupt. 30 Device Ready (READY) This interrupt indicates that the LAN9312 is ready to be accessed after a power-up or reset condition. 29 1588 Interrupt Event (1588_EVNT) This bit indicates an interrupt event from the IEEE 1588 module. This bit ...
Page 175
... Register (FIFO_INT Dropped Frame Interrupt (RXDF_INT) This interrupt is issued whenever a receive frame is dropped by the Host MAC. 5 RESERVED SMSC LAN9312 DESCRIPTION General Purpose Timer Count Register (PMT_CTRL). This for a description of Section 9.8.7, "Transmitter Errors," on page 131 General Purpose TX Data Available Level (FIFO_INT) ...
Page 176
... This interrupt is generated when the RX Status FIFO reaches the programmed level in the Register (FIFO_INT). 2:0 RESERVED Revision 1.7 (06-29-10) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface DESCRIPTION RX Status Level field of the FIFO Level Interrupt 176 DATASHEET Datasheet TYPE DEFAULT R/ SMSC LAN9312 ...
Page 177
... TX Data FIFO Available Interrupt Enable (TDFA_EN Status FIFO Full Interrupt Enable (TSFF_EN Status FIFO Level Interrupt Enable (TSFL_EN Dropped Frame Interrupt Enable (RXDF_INT_EN) SMSC LAN9312 05Ch Size: Interrupt Status Register (INT_STS) bits, which mimic the layout of this register. DESCRIPTION 177 DATASHEET ...
Page 178
... RX Status FIFO Full Interrupt Enable (RSFF_EN Status FIFO Level Interrupt Enable (RSFL_EN) 2:0 RESERVED Revision 1.7 (06-29-10) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface DESCRIPTION 178 DATASHEET Datasheet TYPE DEFAULT R/W 0b R SMSC LAN9312 ...
Page 179
... The value in this field sets the level, in number of DWORD’s, at which the RX Status FIFO Level Interrupt (RSFL) Status FIFO used space is greater than this value, a Interrupt (RSFL) will be generated in the (INT_STS). SMSC LAN9312 068h Size: DESCRIPTION will be generated. When the TX Data FIFO ...
Page 180
... RX End Alignment (RX_EA) This field specifies the alignment that must be maintained on the last data transfer of a buffer. The LAN9312 will add extra DWORD’s of data up to the alignment specified in the table below. The host is responsible for removing these extra DWORD’s. This mechanism can be used to maintain cache line alignment on host processors ...
Page 181
... RX is running. The receiver must be halted, and all data purged before these two bits can be modified. The upper three bits (DWORD offset) may be modified while the receiver is running. Modifications to the upper bits will take affect on the next DWORD read. 7:0 RESERVED SMSC LAN9312 DESCRIPTION 181 DATASHEET TYPE DEFAULT RO ...
Page 182
... All writes to this bit are ignored while this bit is high. Revision 1.7 (06-29-10) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface 070h Size: DESCRIPTION TX Status FIFO Full 182 DATASHEET Datasheet 32 bits TYPE DEFAULT R/W 0b R SMSC LAN9312 ...
Page 183
... No reads should be issued to the RX Data FIFO while this bit is high. Note: Please refer to section Forward," on page 134 of RX_FFWD. 30:0 RESERVED SMSC LAN9312 078h Size: DESCRIPTION Section 9.9.1.1, "Receive Data FIFO Fast for detailed information regarding the use 183 DATASHEET ...
Page 184
... In cases where the payload does not end on a DWORD boundary, the total will be rounded up to the nearest DWORD. Revision 1.7 (06-29-10) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface 07Ch Size: DESCRIPTION 184 DATASHEET Datasheet 32 bits TYPE DEFAULT SMSC LAN9312 ...
Page 185
... This field indicates the amount of space, in DWORD’s, currently used in the TX Status FIFO. 15:0 TX Data FIFO Free Space (TXFREE) This field indicates the amount of space, in bytes, available in the TX Data FIFO. The application should never write more than is available, as indicated by this value. SMSC LAN9312 080h Size: DESCRIPTION 185 DATASHEET 32 bits ...
Page 186
... Revision 1.7 (06-29-10) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface 0A0h Size: DESCRIPTION Interrupt Status Register 186 DATASHEET Datasheet 32 bits TYPE DEFAULT RC 00000000h SMSC LAN9312 ...
Page 187
... The 8-bit value in this field selects which Host MAC CSR will be accessed by the read or write operation. The index of each Host MAC CSR is defined in Section 14.3, "Host MAC Control and Status Registers," on page SMSC LAN9312 0A4h Size: Host MAC CSR Interface Data Register (MAC_CSR_DATA) Section 14.3, " ...
Page 188
... High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface 0A8h Size: Host MAC CSR Interface Command Register Section 14.3, "Host MAC Control and Status 269. For more information on the Host MAC, refer to 112. DESCRIPTION 188 DATASHEET Datasheet 32 bits Chapter 9, "Host TYPE DEFAULT R/W 00000000h SMSC LAN9312 ...
Page 189
... When the Host MAC automatically asserts back pressure, it will be asserted for this period of time. In full-duplex mode, this field has no function and is not used. Please refer to mapping for more information. SMSC LAN9312 0ACh Size: Host MAC Flow Control Register (HMAC_FLOW) for additional information. ...
Page 190
... High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface DESCRIPTION BACKPRESSURE DURATION 100Mbs Mode 5uS 10uS 15uS 25uS 50uS 100uS 150uS 200uS 190 DATASHEET Datasheet TYPE DEFAULT R/W 0b R/W 0b R/W 0b R/W 0b 10Mbs Mode 7.2uS 12.2uS 17.2uS 27.2uS 52.2uS 102.2uS 152.2uS 202.2uS SMSC LAN9312 ...
Page 191
... High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Table 14.2 Backpressure Duration Bit Mapping (continued SMSC LAN9312 BACKPRESSURE DURATION 250uS 300uS 350uS 400uS 450uS 500uS 550uS 600uS 191 DATASHEET 252.2uS 302.2uS 352.2uS 402.2uS 452.2uS 502.2uS 552 ...
Page 192
... High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface 1E0h Size: DESCRIPTION 1588 Interrupt Status and Enable Register General (GPIO_INT_STS_EN). for additional General Purpose I/O register. However, General Purpose I/O is not overridden. 192 DATASHEET Datasheet 32 bits TYPE DEFAULT RO - R/W 00b R/W 0h R/W 0h R/W 1b SMSC LAN9312 ...
Page 193
... As an open-drain driver used for 1588 Clock Events, the corresponding GPIO_EVENT_POL_8 and GPIO_EVENT_POL_9 bits determine when the corresponding pin is driven per the following table: GPIOx Clock Event Polarity SMSC LAN9312 DESCRIPTION 1588 Clock Event Pin State no not driven yes driven low ...
Page 194
... GPDIR bits and the 1588_GPIO_OE bits in the Configuration Register (GPIO_CFG). Revision 1.7 (06-29-10) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface 1E4h Size: DESCRIPTION General Purpose I/O 194 DATASHEET Datasheet 32 bits TYPE DEFAULT R/W 0h SMSC LAN9312 ...
Page 195
... These signals reflect the interrupt status as generated by the GPIOs. These interrupts are configured through the Register (GPIO_CFG). Note: As GPIO interrupts, GPIO inputs are level sensitive and must be active greater than recognized as interrupt inputs. SMSC LAN9312 1E8h Size: Interrupt Status Register Interrupt Enable Register (INT_EN) Chapter 5, "System Interrupts," on page 49 DESCRIPTION ...
Page 196
... Section 4.2.4, "Configuration Straps," on page 40 Revision 1.7 (06-29-10) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface 1BCh Size: DESCRIPTION 164. for more information. for more information. 196 DATASHEET Datasheet 32 bits TYPE DEFAULT RO - R/W Note 14.2 R/W Note 14.3 SMSC LAN9312 ...
Page 197
... High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 14.2.4 EEPROM This section details the EEPROM related System CSR’s. These registers should only be used if an EEPROM has been connected to the LAN9312. Refer to chapter EEPROM Controller," on page 137 of the EEPROM Controller (EPC). 14.2.4.1 EEPROM Command Register (E2P_CMD) Offset: This read/write register is used to control the read and write operations of the serial EEPROM ...
Page 198
... High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface DESCRIPTION [28] Operation 0 READ 1 EWDS 0 EWEN 1 WRITE 0 WRAL 1 ERASE 0 ERAL 1 RELOAD EEPROM Data to be written to the EEPROM EEPROM Data Register (E2P_DATA) should be polled 198 DATASHEET Datasheet TYPE DEFAULT R/W 000b 2 C mode SMSC LAN9312 ...
Page 199
... RELOAD. This bit is cleared when written high. 15:0 EEPROM Controller Address (EPC_ADDRESS) This field is used by the EEPROM Controller to address a specific memory location in the serial EEPROM. This address must be byte aligned. SMSC LAN9312 DESCRIPTION 199 DATASHEET TYPE DEFAULT ...
Page 200
... This field contains the data read from or written to the EEPROM. Revision 1.7 (06-29-10) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface 1B8h Size: EEPROM Command Register (E2P_CMD) DESCRIPTION 200 DATASHEET Datasheet 32 bits TYPE DEFAULT RO - R/W 00h SMSC LAN9312 to ...