LAN9312-NZW SMSC, LAN9312-NZW Datasheet - Page 294

• Manufacturer Part Number: LAN9312-NZW
• Description: Ethernet ICs Hi Per 2 Port 10/100 Ethernet Switch
• Manufacturer: SMSC
• Type: Two Port Managed Ethernet Switchr

Specifications of LAN9312-NZW

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Switches
• Number Of Transceivers: 1
• Standard Supported: 802.3, 802.3u
• Data Rate: 10 Mbps, 100 Mbps
• Supply Voltage (max): 3.3 V
• Supply Voltage (min): 0 V
• Supply Current (max): 186 mA, 295 mA
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Revision 1.7 (06-29-10)
autoneg_strap_x
BITS
4:0
autoneg_strap_x
0
0
0
0
1
1
1
1
Selector Field
This field identifies the type of message being sent by Auto-Negotiation.
00001: IEEE 802.3
0
0
1
Note 14.53 The Pause and Asymmetric Pause bits are loaded into the PHY registers by the EEPROM
Note 14.54 The default value of this bit is determined by the Manual Flow Control Enable Strap
Note 14.55 The default value of this bit is determined by the logical OR of the Auto-Negotiation strap
Note 14.56 The default value of this bit is determined by the logical OR of the Auto-Negotiation strap
Table 14.9 10BASE-T Half Duplex Advertisement Bit Default Value
Table 14.8 10BASE-T Full Duplex Advertisement Default Value
speed_strap_x
Loader.
(manual_FC_strap_x). When the Manual Flow Control Enable Strap is 0, this bit defaults
to 1 (symmetric pause advertised). When the Manual Flow Control Enable Strap is 1, this
bit defaults to 0 (symmetric pause not advertised). Configuration strap values are latched
upon the de-assertion of a chip-level reset as described in
Straps," on page
configuration strap definitions.
(autoneg_strap_x) with the logical AND of the negated speed select strap (speed_strap_x)
and (duplex_strap_x).
strap values are latched upon the de-assertion of a chip-level reset as described in
4.2.4, "Configuration Straps," on page
on page 40
(autoneg_strap_x) and the negated speed strap (speed_strap_x).
default behavior of this bit. Configuration strap values are latched upon the de-assertion
of a chip-level reset as described in
Refer to
definitions.
speed_strap_x
0
0
1
1
0
0
1
1
Section 4.2.4, "Configuration Straps," on page 40
for configuration strap definitions.
0
1
0
DESCRIPTION
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
40. Refer to
duplex_strap_x
DATASHEET
Table 14.8
0
1
0
1
0
1
0
1
294
Section 4.2.4, "Configuration Straps," on page 40
defines the default behavior of this bit. Configuration
Default 10BASE-T Half Duplex (Bit 5) Value
Section 4.2.4, "Configuration Straps," on page
40. Refer to
Default 10BASE-T Full Duplex (Bit 6) Value
Section 4.2.4, "Configuration Straps,"
1
0
1
Section 4.2.4, "Configuration
0
1
0
0
1
1
1
1
TYPE
for configuration strap
R/W
Table 14.9
SMSC LAN9312
DEFAULT
00001b
defines the
Datasheet
Section
40.
for