LAN9312-NZW SMSC, LAN9312-NZW Datasheet - Page 59

Ethernet ICs Hi Per 2 Port 10/100 Ethernet Switch

LAN9312-NZW

Manufacturer Part Number
LAN9312-NZW
Description
Ethernet ICs Hi Per 2 Port 10/100 Ethernet Switch
Manufacturer
SMSC
Type
Two Port Managed Ethernet Switchr
Datasheet

Specifications of LAN9312-NZW

Ethernet Connection Type
10 Base-T, 100 Base-TX
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Product
Ethernet Switches
Number Of Transceivers
1
Standard Supported
802.3, 802.3u
Data Rate
10 Mbps, 100 Mbps
Supply Voltage (max)
3.3 V
Supply Voltage (min)
0 V
Supply Current (max)
186 mA, 295 mA
Maximum Operating Temperature
+ 70 C
Package / Case
TQFP-100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LAN9312-NZW
Manufacturer:
Standard
Quantity:
143
Part Number:
LAN9312-NZW
Manufacturer:
Microchip Technology
Quantity:
10 000
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9312
10
11
1
2
3
4
5
6
7
8
9
-
-
-
-
X
X
1
1
0
0
0
0
0
0
0
0
0
0
0
register. When Auto-negotiation is enabled and the MANUAL_FC_x bit is cleared, the switch port flow
control enables during full-duplex are determined by Auto-negotiation.
Note: The flow control values in the
Note 6.1
Note 6.2
X
X
0
0
1
1
1
1
1
1
1
1
1
1
1
(PHY_AN_AD V_ x)
(VPHY_AN_ADV)
Section 7.2.5.1, "PHY Pause Flow Control," on page 92
Pause Flow Control," on page 98
control settings respectively.
X
X
X
X
0
1
1
1
1
1
1
1
1
1
1
If Auto-negotiation is enabled and complete, but the link partner is not Auto-negotiation
capable, half-duplex is forced via the parallel detect function.
For the Port 1 and Port 2 PHYs, these are the bits from the
Advertisement Register (PHY_AN_ADV_x)
Base Page Ability Register
are the local/partner swapped outputs from the bits in the
Advertisement Register (VPHY_AN_ADV)
Base Page Ability Register
"Virtual PHY Auto-Negotiation," on page 96
X
X
X
X
X
0
1
1
1
1
1
1
1
1
1
Table 6.1 Switch Fabric Flow Control Enable Logic
Half (
Half
Half
Half
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
are not affected by the values of the manual flow control register. Refer to
Note
X
an d
6.1)
DATASHEET
Virtual PHY Au to -N egotia tio n Advertisement Register
(PHY_AN_LP_BASE_ABILITY_x). For the Virtual PHY, these
X
X
X
X
X
X
X
0
0
0
0
1
1
1
1
(VPHY_AN_LP_BASE_ABILITY). Refer to
59
for additional information on PHY and Virtual PHY flow
Port x PHY Auto-Negotiation Advertisement Register
X
X
X
X
X
X
X
X
0
1
1
1
0
1
1
and
and
for more information.
Virtual PHY Auto-Negotiation Link Partner
Port x PHY Auto-Negotiation Link Partner
X
X
X
X
X
X
X
X
0
1
1
0
1
0
0
and
Section 7.3.1.3, "Virtual PHY
Virtual PHY Auto-Negotiation
Port x PHY Auto-Negotiation
X
X
X
X
X
X
X
X
X
X
X
0
1
0
1
Revision 1.7 (06-29-10)
RX_FC_x
RX_FC_x
0
0
0
0
0
0
0
0
0
0
1
0
1
Section 7.3.1,
BP_EN_x
BP_EN_x
BP_EN_x
BP_EN_x
TX_FC_x
TX_FC_x
0
0
0
0
1
0
1
0
0

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