LAN9312-NZW SMSC, LAN9312-NZW Datasheet - Page 175

• Manufacturer Part Number: LAN9312-NZW
• Description: Ethernet ICs Hi Per 2 Port 10/100 Ethernet Switch
• Manufacturer: SMSC
• Type: Two Port Managed Ethernet Switchr

Specifications of LAN9312-NZW

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Switches
• Number Of Transceivers: 1
• Standard Supported: 802.3, 802.3u
• Data Rate: 10 Mbps, 100 Mbps
• Supply Voltage (max): 3.3 V
• Supply Voltage (min): 0 V
• Supply Current (max): 186 mA, 295 mA
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9312
BITS
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
GP Timer (GPT_INT)
This interrupt is issued when the
(GPT_CNT)
RESERVED
Power Management Interrupt Event (PME_INT)
This interrupt is issued when a Power Management Event is detected as
configured in the
interrupt functions independent of the PME signal, and will still function if
the PME signal is disabled. Writing a '1' clears this bit regardless of the
state of the PME hardware signal. In order to clear this bit, all unmasked
bits in the
cleared.
Note:
TX Status FIFO Overflow (TXSO)
This interrupt is generated when the TX Status FIFO overflows.
Receive Watchdog Time-out (RWT)
This interrupt is generated when a packet larger than 2048 bytes has been
received by the Host MAC.
Note:
Receiver Error (RXE)
Indicates that the Host MAC receiver has encountered an error. Please
refer to
the conditions that will cause an RXE.
Transmitter Error (TXE)
When generated, indicates that the Host MAC transmitter has encountered
an error. Please refer to
for a description of the conditions that will cause a TXE.
GPIO Interrupt Event (GPIO)
This bit indicates an interrupt event from the General Purpose I/O. The
source of the interrupt can be determined by polling the
I/O Interrupt Status and Enable Register (GPIO_INT_STS_EN)
RESERVED
TX Data FIFO Overrun Interrupt (TDFO)
This interrupt is generated when the TX Data FIFO is full, and another write
is attempted.
TX Data FIFO Available Interrupt (TDFA)
This interrupt is generated when the TX Data FIFO available space is
greater than the programmed level in the
the
TX Status FIFO Full Interrupt (TSFF)
This interrupt is generated when the TX Status FIFO is full.
TX Status FIFO Level Interrupt (TSFL)
This interrupt is generated when the TX Status FIFO reaches the
programmed level in the
Register
RX Dropped Frame Interrupt (RXDF_INT)
This interrupt is issued whenever a receive frame is dropped by the Host
MAC.
RESERVED
FIFO Level Interrupt Register
Section 9.9.5, "Receiver Errors," on page 136
The Interrupt De-assertion interval does not apply to the PME
interrupt.
This can occur when the switch engine adds a tag to a non-tagged
jumbo packet that is originally larger than 2044 bytes.
(FIFO_INT).
Power Management Control Register (PMT_CTRL)
wraps past zero to FFFFh.
Power Management Control Register
Section 9.8.7, "Transmitter Errors," on page 131
TX Status Level
DESCRIPTION
General Purpose Timer Count Register
(FIFO_INT).
DATASHEET
TX Data Available Level
field of the
175
FIFO Level Interrupt
for a description of
(PMT_CTRL). This
General Purpose
must first be
field of
R/WC
R/WC
R/WC
R/WC
R/WC
R/WC
R/WC
R/WC
R/WC
R/WC
R/WC
TYPE
RO
RO
RO
RO
Revision 1.7 (06-29-10)
DEFAULT
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
-
-
-