LAN9312-NZW SMSC, LAN9312-NZW Datasheet - Page 174

• Manufacturer Part Number: LAN9312-NZW
• Description: Ethernet ICs Hi Per 2 Port 10/100 Ethernet Switch
• Manufacturer: SMSC
• Type: Two Port Managed Ethernet Switchr

Specifications of LAN9312-NZW

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Switches
• Number Of Transceivers: 1
• Standard Supported: 802.3, 802.3u
• Data Rate: 10 Mbps, 100 Mbps
• Supply Voltage (max): 3.3 V
• Supply Voltage (min): 0 V
• Supply Current (max): 186 mA, 295 mA
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Revision 1.7 (06-29-10)
14.2.1.2
BITS
31
30
29
28
27
26
25
24
23
22
21
20
Software Interrupt (SW_INT)
This interrupt is generated when the SW_INT_EN bit of the
Register (INT_EN)
Device Ready (READY)
This interrupt indicates that the LAN9312 is ready to be accessed after a
power-up or reset condition.
1588 Interrupt Event (1588_EVNT)
This bit indicates an interrupt event from the IEEE 1588 module. This bit
should be used in conjunction with the
Register (1588_INT_STS_EN)
event within the 1588 module.
Switch Fabric Interrupt Event (SWITCH_INT)
This bit indicates an interrupt event from the Switch Fabric. This bit should
be used in conjunction with the
(SW_IPR)
Fabric.
Port 2 PHY Interrupt Event (PHY_INT2)
This bit indicates an interrupt event from the Port 2 PHY. The source of the
interrupt can be determined by polling the
Flags Register
Port 1 PHY Interrupt Event (PHY_INT1)
This bit indicates an interrupt event from the Port 1 PHY. The source of the
interrupt can be determined by polling the
Flags Register
TX Stopped (TXSTOP_INT)
This interrupt is issued when STOP_TX bit in
Register (TX_CFG)
RX Stopped (RXSTOP_INT)
T
RX Dropped Frame Counter Halfway (RXDFH_INT)
This interrupt is issued when the
Register (RX_DROP)
80000000h).
RESERVED
TX IOC Interrupt (TX_IOC)
This interrupt is generated when a buffer with the IOC flag set has been
fully loaded into the TX Data FIFO.
RX DMA Interrupt (RXD_INT)
This interrupt is issued when the amount of data programmed in the RX
DMA Count (RX_DMA_CNT) field of the
(RX_CFG)
his interrupt is issued when the Host MAC receiver is halted.
Interrupt Status Register (INT_STS)
This register contains the current status of the generated interrupts. A value of 1 indicates the
corresponding interrupt conditions have been met, while a value of 0 indicates the interrupt conditions
have not been met. The bits of this register reflect the status of the interrupt source regardless of
whether the source has been enabled as an interrupt in the
indicated as R/WC, writing a 1 to the corresponding bits acknowledges and clears the interrupt.
to determine the source of the interrupt event within the Switch
Offset:
has been transferred out of the RX Data FIFO.
(PHY_INTERRUPT_SOURCE_x).
(PHY_INTERRUPT_SOURCE_x).
is set high. Writing a one clears this interrupt.
is set, and the Host MAC transmitter is halted.
counts past its halfway point (7FFFFFFFh to
058h
DESCRIPTION
to determine the source of the interrupt
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Switch Global Interrupt Pending Register
Host MAC RX Dropped Frames Counter
DATASHEET
1588 Interrupt Status and Enable
Receive Configuration Register
Port x PHY Interrupt Source
Port x PHY Interrupt Source
174
Transmit Configuration
Size:
Interrupt Enable
Interrupt Enable Register
32 bits
R/WC
R/WC
R/WC
R/WC
R/WC
R/WC
R/WC
TYPE
RO
RO
RO
RO
RO
(INT_EN). Where
SMSC LAN9312
DEFAULT
Datasheet
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
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