UPB1009K NEC, UPB1009K Datasheet

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... MHz, f REFin : On-chip switchable frequency divider (1/N = 100, 3/256, 9/1024, 65/4096) : On-chip 4-bit A/D converter : On-chip VCO tank circuit and 2ndIF filter : V = 2 26.0 mA TYP 3 100 44-pin plastic QFN UPB1009K = 4.092 MHz 2ndIFin = 62.980 MHz 2.556 MHz 1stIFin 2ndIFin ...

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... PB1009K-E1-A 44-pin plastic QFN Remark To order evaluation samples, contact your nearby sales office. Part number for sample order: µ PB1009K 2 Supplying Form • wide embossed taping • Pin 1 indicates pull-out direction of tape • Qty 1.5 kpcs/reel, Dry pack specification UPB1009K ...

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... This diagram does not present the actual application circuits (V) (mA) (dB) 2.7 to 3.3 26.0 44-pin plastic QFN 2.7 to 3.3 18.0 100 to 36-pin plastic QFN 120 2.7 to 3.3 25.0 100 to 120 36-pin plastic QFN 36-pin plastic QFN UPB1009K Package Status New Device Available 3 ...

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... PIN CONNECTION AND INTERNAL BLOCK DIAGRAM 4 UPB1009K ...

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... Power supply voltage pin for RF mixer. CC Connect a bypass capacitor to this pin to reduce the high-frequency impedance. 41 1stIFout Output pin of RF mixer. Insert an IFSAW filter between this pin and pin 37. The VCO oscillation signal can be monitored on this pin. UPB1009K Internal Equivalent Circuit 5 ...

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... Power supply voltage pin of PLL. CC Connect a bypass capacitor to this pin to reduce the high-frequency impedance. 15 PLLGND Ground pin of PLL. 16 CLKout Clock (f ) output pin (IC test pin). TCXO 6 Internal Equivalent Circuit TCXO : 16.368, 16.384 MHz TCXO : 19.2 MHz TCXO : 14.4 MHz TCXO : 26 MHz = I = 0.45 sink source UPB1009K ...

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... VCO2 Leave this pin open when the µ PB1009K is mounted on board. 10 LoGND Ground pin of VCO. 17 IFGND Ground pin of IF block. 18 2ndIFout Output pin of IF amplifier. 38 1stIFin Input pin of second IF mixer. 39 IFV Power supply voltage pin of IF block. CC UPB1009K Internal Equivalent Circuit 7 ...

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... A/D converter via a bypass capacitor to reduce the high-frequency impedance. 26 GNDsub Ground pin of CMOS substrate Digital signal output pins LSB = D0, MSB = SCKin Sampling clock signal input pin. 32 AGCin AGC control pulse signal input pin. 33 AGCout AGC control signal output pin. 8 UPB1009K Internal Equivalent Circuit ...

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... Ground pin for power control logic. 36 PD1 Low : PD1 : L 37 PD2 0 to 0.3 (V) PD2 : L High : PD1 : L V − 0.3 to PD2 : (V) PD1 : H CC PD2 : L PD1 : H PD2 : H Internal Equivalent Circuit Sleep mode (all circuits off). Warm-up mode (PLL on). Calibration mode . Active mode (all circuits on). UPB1009K 9 ...

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... TCXO − 0 − V − 0.3 − − V − 0.3 − CC UPB1009K Ratings Unit 3.6 V 100 mA 266 mW −40 to +85 °C −55 to +125 °C MAX. Unit 3.3 V +85 °C MHz − MHz − ...

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... H L OFF OFF L L OFF OFF MODE Test Conditions 1/N Phase Comparison Frequency PD1 PD2 L L 1/100 L H 3/256 H L 9/1024 H H 65/4096 They are respectively 62.98 MHz UPB1009K PLL Block OFF 16.368 MHz 16.384 MHz 19.2 MHz 14.4 MHz 26 MHz 1 1 ...

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... MHz, 1 576.42 MHz RFin Calculated from S-parameter where input DC cut capacitance = 1 nF, output load L = 100 n, and DC cut capacitance = 1 nF ana ♦ GNDana) in the sleep mode, and the sleep mode DD ) and GND is 10 µ A maximum. UPB1009K MIN. TYP. MAX. Unit 1.3 2.2 3 ...

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... V 1stIFin1 AGC f = 61.38 MHz V = 1.5 V 1stIFin2 AGC f = 65.472 MHz V = 2.5 V 2ndLO AGC Calculated from S-parameter where input DC cut capacitance = 1 nF and output DC cut capacitance = 100 nF UPB1009K MIN. TYP. MAX. Unit 2.0 2.5 3.0 mA 14.0 16.1 19.0 dB 12.8 16.0 dB − −4.0 − ...

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... CC V Center frequency When PLL is Locked Δ 10 kHz DC characteristics IF = 5.17 MHz 20.48 MHz IF = 5.17 MHz 20.48 MHz ENOB = (SINAD−1.763)/6. 5.17 MHz 20.48 MHz Second-degree to fifth-degree distortion components UPB1009K MIN. TYP. MAX. Unit 8.0 9.5 10 −0.55 −0.45 −0.35 0.35 ...

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... The following table shows each timing parameter for reference purposes. Symbol Parameter T Output Delay pF Pipeline Delay pld T Sampling Delay ds (Aperture Delay) T Output Hold Time oh Test Conditions MIN. TYP. = 19.2 MHz − − clk 1.5 − 2 − 2 − UPB1009K MAX. Unit 12 ns clock − ns − ns − ...

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... The output code of the ADC of the µ PB1009K is undefined for 7.5 clocks after the power-down signal is cleared when the ADC returns from the power-down status to normal operation The output data is undefined from the start of the power-down operation to the 7.5th clock from the falling edge of the clock at which the power-down operation is cleared UPB1009K ...

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... TYPICAL CHARACTERISTICS (T  IC TOTAL CHARACTERISTICS  Remark The graphs indicate nominal characteristics. = +25° 3.0 V, unless otherwise specified UPB1009K 1 7 ...

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... PRE-AMPLIFIER BLOCK  Remark The graphs indicate nominal characteristics CHARACTERISTICS  UPB1009K ...

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... RF MIX BLOCK CHARACTERISTICS  Remark The graphs indicate nominal characteristics. UPB1009K 1 9 ...

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... IF BLOCK CHARACTERISTICS  Remark The graphs indicate nominal characteristics UPB1009K ...

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... VCO MODULATION SENSITIVITY  C/N CHARACTERISTICS   Remark The graphs indicate nominal characteristics. CHARACTERISTICS  UPB1009K 2 1 ...

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... SINAD CHARACTERISTICS  MHz)  Remark The graphs indicate nominal characteristics A/D CONVERTOR (IFin = 5.17 MHz, SCLKin = 20.48 UPB1009K ...

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... MEASUREMENT CIRCUIT UPB1009K 2 3 ...

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... VCOc 19 Sampling Signal Input CPout 20 AGC Input MS2 21 AGC Control Voltage Output REFin 22 PD1 Output (Default onboard : GND) CLKout 23 PD1 Output (Default on board : V 2ndIFout 24 1stIF Input 2ndIFin 25 1stIF Output DCOFFout UPB1009K Pin Name DCOFFin SCKin AGCin AGCout PD1 ) PD2 CC 1stIFin 1stIFout ...

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... APPLICATION CIRCUIT PD1 PD2 Power-down mode 0 0 Sleep mode (full off Warm-up mode (PLL on Calibration mode (PLL on Active mode (full on) MS1 MS2 TCXO 0 0 16.368/16.384 MHz 0 1 19.2 MHz 1 0 14.4 MHz 1 1 26.0 MHz UPB1009K N 100 256/3 1024/9 4096/ ...

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... PACKAGE DIMENSIONS 44-PIN PLASTIC QFN (UNIT: mm) Caution The island pins located on the corners are needed to fabricate products in our plant, but do not serve any other function. Consequently the island pins should not be soldered and should remain non-connection pins UPB1009K ...

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... UPB1009K Condition Symbol IR260 VP215 WS260 HS350 2 7 ...

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Subject: Compliance with EU Dire ctives CEL certifies, to its kno w ledge, that semicondu ctor and laser products detailed below are compliant with the requirements of European Union (EU) Directive 2002/95/EC Restriction on Use of Hazardous Substances in electrical ...