LX128EC-32F208C Lattice, LX128EC-32F208C Datasheet - Page 57

• Manufacturer Part Number: LX128EC-32F208C
• Description: Analog & Digital Crosspoint ICs E-Series, 128 I/O Switch Matrix, 1.8V, 3.2ns
• Manufacturer: Lattice

Specifications of LX128EC-32F208C

• Maximum Dual Supply Voltage: 1.95 V
• Minimum Dual Supply Voltage: 1.65 V
• Mounting Style: SMD/SMT
• Number Of Arrays: 1
• Operating Supply Voltage: 1.8 V
• Supply Type: Triple
• Configuration: 128 x 128
• Package / Case: FPBGA-208
• Data Rate: 21 Gbps
• Input Level: Bus LVDS, LVCMOS, LVDS, LVPECL, LVTTL
• Output Level: Bus LVDS, LVCMOS, LVDS, LVPECL, LVTTL
• Maximum Operating Temperature: + 90 C
• Minimum Operating Temperature: 0 C
• Product: Digital Crosspoint
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
ispGDX2-64 Logic Signal Connections (Continued)
SEL0
SEL1
BK4_IO0/CLK_OUT2
BK4_IO1
GND
BK4_IO2
BK4_IO3
GND
BK4_IO4
BK4_IO5
BK4_IO6
BK4_IO7
TMS
TDI
GND
TDO
TOE
BK5_IO0
BK5_IO1
BK5_IO2
BK5_IO3/Vref(4,5)
GND
BK5_IO4
BK5_IO5
GND
BK5_IO6
BK5_IO7
GCLK/CE0
GCLK/CE1
BK6_IO0
BK6_IO1
GND
BK6_IO2
BK6_IO3
GND
BK6_IO4/Vref(Bank6,7)
BK6_IO5
BK6_IO6
BK6_IO7/PLL_FBK2
BK7_IO0
BK7_IO1
BK7_IO2
BK7_IO3/PLL_RST2
GND
BK7_IO4
BK7_IO5
Signal Name
sysIO
Bank
4
4
4
4
4
4
4
4
5
5
5
5
5
5
5
5
6
6
6
6
6
6
6
6
7
7
7
7
7
4
4
5
5
6
6
7
7
-
-
-
-
-
-
-
-
-
Pair/Polarity
CLK0P
CLK0N
LVDS
16N
17N
18N
19N
20N
21N
22N
23N
24N
25N
26N
27N
28N
29N
30N
16P
17P
18P
19P
20P
21P
22P
23P
24P
25P
26P
27P
28P
29P
30P
-
-
-
-
-
-
-
-
-
-
-
-
Block
GDX
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1A
1B
1B
1B
1B
1B
1B
1B
1B
1B
1B
1B
1B
1B
1B
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
MRB
10
11
12
13
14
15
10
11
12
13
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
-
-
-
-
-
-
-
-
-
-
-
-
-
-
HSI1A_CDRRSTb
SS_CLKOUT1N
SS_CLKOUT1P
SERDES Mode
FIFO2_STRDb
HSI1A_SOUTN
HSI1B_SOUTN
HSI1B_SOUTP
FIFO3_STRDb
HSI1_CSLOCK
HSI1A_SOUTP
HSI1B_SYDT
HSI1A_SYDT
SS_CLKIN1P
SS_CLKIN1N
HSI1A_SINN
HSI1A_SINP
HSI1B_SINP
HSI1B_SINN
54
I/O Pin
Note 4
Note 4
CAL
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
5
5
6
6
HSI1A_RXD9/TXD9
HSI1A_RXD8/TXD8
HSI1A_RXD7/TXD7
HSI1A_RXD6/TXD6
HSI1A_RXD5/TXD5
HSI1A_RXD4/TXD4
HSI1A_RXD3/TXD3
HSI1A_RXD2/TXD2
HSI1A_RXD1/TXD1
HSI1A_RXD0/TXD0
HSI1B_RXD9/TXD9
HSI1B_RXD8/TXD8
HSI1B_RXD7/TXD7
HSI1B_RXD6/TXD6
HSI1B_RXD5/TXD5
HSI1B_RXD4/TXD4
HSI1B_RXD3/TXD3
HSI1B_RXD2/TXD2
HSI1B_RXD1/TXD1
HSI1B_RXD0/TXD0
HSI1A_RECCLK
HSI1B_RECCLK
SERDES Mode
HSI1A_SYDT
HSI1B_SYDT
I/O Cell
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ispGDX2 Family Data Sheet
2
5
5
FIFO2_DIN9/DOUT9
FIFO2_DIN8/DOUT8
FIFO2_DIN7/DOUT7
FIFO2_DIN6/DOUT6
FIFO2_DIN5/DOUT5
FIFO2_DIN4/DOUT4
FIFO2_DIN3/DOUT3
FIFO2_DIN2/DOUT2
FIFO2_DIN1/DOUT1
FIFO2_DIN0/DOUT0
FIFO3_DIN9/DOUT9
FIFO3_DIN8/DOUT8
FIFO3_DIN7/DOUT7
FIFO3_DIN6/DOUT6
FIFO3_DIN5/DOUT5
FIFO3_DIN4/DOUT4
FIFO3_DIN3/DOUT3
FIFO3_DIN2/DOUT2
FIFO3_DIN1/DOUT1
FIFO3_DIN0/DOUT0
FIFO2_FIFORSTb
FIFO Mode I/O
FIFO2_EMPTY
FIFO3_EMPTY
FIFO2_FULL
Cell/Pin
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
3
fpBGA
GND
GND
GND
GND
GND
GND
GND
GND
100
G3
G2
D6
D5
C5
D4
C4
A6
A5
A4
A3
C1
C2
C3
D1
D3
D2
E2
E3
E4
G1
H1
H2
K2
K3
G4
H4
B5
B3
A2
B1
B2
F4
F3
F2
J3
J4
J1