LX128EC-32F208C Lattice, LX128EC-32F208C Datasheet - Page 62

• Manufacturer Part Number: LX128EC-32F208C
• Description: Analog & Digital Crosspoint ICs E-Series, 128 I/O Switch Matrix, 1.8V, 3.2ns
• Manufacturer: Lattice

Specifications of LX128EC-32F208C

• Maximum Dual Supply Voltage: 1.95 V
• Minimum Dual Supply Voltage: 1.65 V
• Mounting Style: SMD/SMT
• Number Of Arrays: 1
• Operating Supply Voltage: 1.8 V
• Supply Type: Triple
• Configuration: 128 x 128
• Package / Case: FPBGA-208
• Data Rate: 21 Gbps
• Input Level: Bus LVDS, LVCMOS, LVDS, LVPECL, LVTTL
• Output Level: Bus LVDS, LVCMOS, LVDS, LVPECL, LVTTL
• Maximum Operating Temperature: + 90 C
• Minimum Operating Temperature: 0 C
• Product: Digital Crosspoint
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
ispGDX2-128 Logic Signal Connections (Continued)
GND
BK6_IO12
BK6_IO13
BK6_IO14
BK6_IO15 / VREF6
TDI
GOE0
GND
BK7_IO0 / VREF7
BK7_IO1
BK7_IO2
BK7_IO3
BK7_IO4
BK7_IO5
BK7_IO6
BK7_IO7
BK7_IO8
BK7_IO9
BK7_IO10
BK7_IO11
GND
BK7_IO12
BK7_IO13
BK7_IO14
BK7_IO15
1. The signals in this column route to/from the assigned pins of the associated I/O cell.
2. The signals in this column use the I/O cell. If a receiver signal is present in the I/O cell, the associated pin is available for output only. When
3. The DOUT outputs are routed to GRP through the input register of the cell and the DIN inputs are routed direct from the associated pins in
4. If the Source Synchronous Receiver is used in the HSI Block, this pin is unavailable for another use and must be left unconnected.
5. The SYDT signal has two routing options. If direct output through the dedicated pin is used, the I/O cell (the whole HSI Block) is not avail-
6. FIFO_STRDb flag output is used in SERDES with FIFO Mode only.
7. sysHSI Source Synchronous Receive Mode is not available for channel 1A.
transmit data (TXD) is present in the cell, the associated pin is available for input only.
FIFO only mode. In SERDES with FIFO mode, the FULL and EMPTY flags are routed to the associated pins through the output MUX and
the pins.
able for transmitter. The SYDT in the I/O Cell column is routed to the GRP through the input register of the cell and frees the I/O cell for
transmitter.
Signal Name
sysIO
Bank
6
6
6
6
6
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
-
-
Pair/Polarity
LVDS
54N
55N
56N
57N
58N
59N
60N
61N
62N
63N
54P
55P
56P
57P
58P
59P
60P
61P
62P
63P
Block MRB
GDX
3A
3A
3A
3A
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
-
-
-
-
-
12
13
14
15
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
-
-
-
-
-
HSI3B_CDRRSTb
FIFO3B_STRDb
SERDES Mode
HSI3B_SOUTP
HSI3B_SOUTN
HSI3B_SYDT
HSI3B_SINP
HSI3B_SINN
59
I/O Pin
Note 4
Note 4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
5
6
HSI3A_RXD2/TXD2
HSI3A_RXD1/TXD1
HSI3A_RXD0/TXD0
HSI3B_RXD9/TXD9
HSI3B_RXD8/TXD8
HSI3B_RXD7/TXD7
HSI3B_RXD6/TXD6
HSI3B_RXD5/TXD5
HSI3B_RXD4/TXD4
HSI3B_RXD3/TXD3
HSI3B_RXD2/TXD2
HSI3B_RXD1/TXD1
HSI3B_RXD0/TXD0
HSI3B_RECCLK
SERDES Mode
HSI3A_SYDT
HSI3B_SYDT
I/O Cell
-
-
-
-
-
-
-
-
-
ispGDX2 Family Data Sheet
2
5
5
FIFO3A_DIN2/DOUT2
FIFO3A_DIN1/DOUT1
FIFO3A_DIN0/DOUT0
FIFO3B_DIN9/DOUT9
FIFO3B_DIN8/DOUT8
FIFO3B_DIN7/DOUT7
FIFO3B_DIN6/DOUT6
FIFO3B_DIN5/DOUT5
FIFO3B_DIN4/DOUT4
FIFO3B_DIN3/DOUT3
FIFO3B_DIN2/DOUT2
FIFO3B_DIN1/DOUT1
FIFO3B_DIN0/DOUT0
FIFO3B_FIFORSTb
FIFO3B_ EMPTY
FIFO Mode I/O
FIFO3A_ FULL
FIFO3B_FULL
Cell/Pin
-
-
-
-
-
-
-
-
3
fpBGA
GND
GND
GND
208
N2
P1
N3
R3
N5
P5
R4
R5
N7
P7
R6
R7
L3
P2
T8
T2
P4
T3
T4
P6
T6
T7