E-STE10/100A STMicroelectronics, E-STE10/100A Datasheet
E-STE10/100A
Specifications of E-STE10/100A
Related parts for E-STE10/100A
E-STE10/100A Summary of contents
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... It was designed with advanced CMOS technology to provide glueless 32-bit bus master interface for PCI bus, boot ROM interface, CSMA/CD protocol for fast ethernet, as well as the physical media interface for 100BASE-TX of IEEE802.3u and 10BASE-T of IEEE802.3. The auto-negotiation function is also supported for speed and duplex detection ...
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... STE10/100A configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.1.1 4.2 PCI control/status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4.3 Transceiver(XCVR) registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 2/82 Descriptor structure types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Descriptor management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Transmit scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Transmit pre-fetch data flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Transmit early interrupt scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 MAC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Transceiver operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Flow control in full duplex application . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Reset whole chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Reset transceiver only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Power states ...
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... STE10/100A 4.4 Descriptors and buffer management . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 4.4.1 4.4.2 5 General EEPROM format description . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6 Electrical specifications and timings . . . . . . . . . . . . . . . . . . . . . . . . . . 71 6.1 Timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 7 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Receive descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Transmit descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Contents 3/82 ...
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... Overview 1 Overview 1.1 Block diagrams Figure 1. STE10/100A block diagram Flow control EMI Figure 2. STE10/100A system diagram PCI interface 4/82 Manchester encoder 4B/5B DMA Auto-negociation Tx FiFo 5B/4B Rx FiFo 100 clock recovery Serial EEPROM Boot ROM STE10/100A LEDs 25MHz crystal STE10/100A 10 TX filter ...
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... FIFO ● Provides independent transmission and receiving FIFOs, each 2k bytes long ● Pre-fetches up to two transmit packets to minimize inter frame gap (IFG) to 0.96us ● Retransmits collided packet without reload from host memory within 64 bytes. ● Automatically retransmits FIFO under-run packet with maximum drain threshold until 3rd time retry failure threshold of next packet ...
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... Activity (Blinks at 10Hz when receiving or transmitting) FD (Remains on when in full duplex mode) or when collision detected (Blinks at 20Hz) ● LED is used, then: Pull the pins 90, 91 high with 4.7K resistor (see STE10/100A evaluation board schematics for details) 6/82 STE10/100A ...
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... STE10/100A 2 Pin description Figure 3. Pin connection Pin description 7/82 ...
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... PCI bus granted. This signal indicates that the STE10/100A I has been granted ownership of the PCI bus as a result of a bus request. PCI bus request. STE10/100A asserts this line when it needs O access to the PCI Bus. ...
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... PAR for read data phase. ROM data bus Provides up to 128Kbit EPROM or flash-ROM application space. This pin can be programmed as mode 2 LED display for full I/O duplex or collision status. It will be driven (LED on) continually when a full duplex configuration is detected will be driven blinking frequency when a collision status is detected in the half duplex configuration ...
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... This pin can be programmed as mode 1 or mode 2: For mode 1: LED display for 100M b/s or 10M b/s speed. This pin will be driven on continually when the 100M b/s network operating O speed is detected. For mode 2: LED display for 100Ms/s link status ...
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... This pin will be driven blinking frequency O when a collision status is detected in the half duplex configuration. For mode 2: LED display for 10Ms/s link status. This pin will be driven on continually when 10Mb/s network operating speed is detected. When this pin is asserted, it indicates an auxiliary power I source is supported from the system ...
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... Set physical address (CSR25, 26) Need set Prepare transmit descriptor and buffer Prepare receive descriptor and buffer Install NIC ISR function Open NIC interrupt Enable Tx & Rx functions 12/82 Yes Program the media type to XR0 No Set multimedia address table No Yes A END STE10/100A (Force media) ...
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... STE10/100A transfers the data packet from its receive FIFO to receive buffers in the host’s memory. The STE10/100A makes use of descriptors, data structures which are built in host memory and contain pointers to the transmit and receive buffers and maintain packet and frame parameters, status, and other information vital to controlling network operation ...
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... Functional description Chain structure There is only one buffer per descriptor in chain structure. Figure 6. Frame buffer chain structure CSR3 or CSR4 Descriptor pointer 14/82 Descriptor own --- Data buffer Length 1 Buffer1 pointer Next pointer own --- Length 2 Buffer1 pointer Next pointer own --- Length 3 Buffer1 pointer Next pointer ...
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... STE10/100A 3.2.2 Descriptor management OWN bit = 1, ready for network side access OWN bit = 0, ready for host side access Transmit descriptors Figure 7. Transmit descriptor management Ext packet to be transmitted Ext packet to be transmitted Own bit=1, Own bit=1, packet 1 and packet 2 packet 1 and packet 2 ...
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... Functional description Receive descriptors Figure 8. Receive descriptor management Own bit = 1 Own bit = 1 Next descriptor ready Next descriptor ready for incoming packet for incoming packet Filled descriptor pointer Filled descriptor pointer 16/ Packet 2 Packet Packet 1 Packet 1 • • • • • • End of ring ...
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... STE10/100A 3.3 Transmit scheme and transmit early interrupt 3.3.1 Transmit scheme Figure 9. Transmit scheme Own = 0 Own = 0 Exit Exit Back-off Back-off Initialize descriptor Initialize descriptor Place data in host memory Place data in host memory Set own bit to 1 Set own bit to 1 Write Tx demand poll command ...
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... FIFO-to-host memory operation (2nd packet) Place the 3rd packet data into host memory FIFO-to-host memory operation (3rd packet) 3.3.3 Transmit early interrupt scheme Figure 11. Transmit normal interrupt and early interrupt comparison Host to TX-FIFO memory Host to TX-FIFO memory operation operation Transmit data from FIFO to media ...
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... STE10/100A 3.4 Receive scheme and receive early interrupt scheme The following figure shows the difference of timing without early interrupt and with early interrupt. Figure 12. Receive data flow (without early interrupt and with early interrupt) Incoming packet Receive FIFO operation FIFO-to-host memory operation ...
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... Receive data decapsulation When operating in 100BASE-TX mode the STE10/100A detects a JK code in a preamble as well code at the packet end code is not detected, the STE10/100A will abort the reception of the frame and wait for a new JK code detection code is not detected, the STE10/100A will report a CRC error. ...
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... Diego, CA92128. Tel: (619) 674-8100. Data code-groups encoder In normal MII mode applications, the transceiver receives nibble type 4B data via the TxD0~3 inputs of the MII. These inputs are sampled by the transceiver on the rising edge of Tx-clk and passed to the 4B/5B encoder to generate the 5B code-group used by 100BASE- TX. ...
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... The bit stream will be further converted from NRZ to NRZI format, unless the conversion function is bypassed by clearing ENRZI (bit 7 of XR10 After NRZI conversion, the NRZI bit stream is passed through MLT3 encoder to generate the TP-PMD specified MLT3 code. By using MLT3 code, the frequency and energy content of the transmission signal is reduced in the UTP, making the system more easily compliant to FCC EMI specifications ...
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... The transceiver provides internal loop-back (also called transceiver loop-back) operation for both 100BASE-TX and 10BASE-T operation. The loop-back function can be enabled by setting XLBEN (bit 14 of XR0 loop-back mode, the TX± and RX± lines are isolated from the media. The transceiver also provides remote loop-back operation for 100BASE-TX operation ...
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... XR0). During auto-negotiation information is exchanged with the network partner using fast link pulses (FLPs burst of link pulses. There are 16 bits of signaling information contained in the link pulses which advertise to the remote partner the capabilities which are represented by the contents of ANA (register XR4). According to this information the partners find out their highest common capabilities by following the priority sequence listed below: – ...
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... PAUSE time is specified in the MAC control parameters field with 2 octets, representing an unsigned integer, in units of slot-times. The range of possible PAUSE times 65535 slot-times. A valid PAUSE frame issued by a MAC control client (for example, a switch or a bridge) would contain: – ...
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... MAC control parameters field. When the timer value reaches zero, the STE10/100A exits the PAUSE state. However, a PAUSE frame will not affect the transmission of a frame that has been submitted to the MAC (i.e., once a transmit out of the MAC is begun, it can’t be interrupted). Conversely, the STE10/100A will not begin to transmit a frame more than one slot-time after valid PAUSE frame is received a with a non-zero PAUSE time ...
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... SWR) and set XRST(XR0, bit 15) to reset the transceivers. 3.7.2 Reset transceiver only When XRST (bit 15 of XR0) is set to 1, the transceiver will reset its circuits, will initialize its registers to their default values, and clear XRST. Functional description ...
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... Power states DO (Fully on) In this state the STE10/100A operates with full functionality and consumes normal power. While in the D0 state, if the PCI clock is lower than 16MHz, the STE10/100A may not receive or transmit frames properly. D1, D2, and D3 hot In these states, the STE10/100A doesn’t respond to any accesses except configuration space and full function context in place ...
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... STE10/100A D3 (Software visible D3) hot When the STE10/100A is brought back to D0 from D3hot the software must perform a full initialization. The STE10/100A in the D3hot state responds to configuration cycles as long as power and clock are supplied. This requires the device to perform an internal reset and return to a power-up reset condition without the RST# pin asserted ...
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... They include 7 basic registers which are defined according to clause 22 “Reconciliation Sub-layer and Media Independent Interface” and clause 28 “Physical Layer link signaling for 10 Mb/s and 100 Mb/s auto-negotiation on twisted pair” of the IEEE802.3u standard. In addition, 4 special registers are provided for advanced chip control and status. ...
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... Max_Lat 40h Reserved 80h c0h c4h 1. Automatically recalled from EEPROM when PCI reset is deserted DS(40h), bit15-8, is read/write able register SIG(80h) is hard wired register, read only ----------- b16 Device ID* Status Subclass code ------ ------ Latency timer Base I/O address ...
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... Registers and descriptors description 4.1.1 STE10/100A configuration registers description Table 6. Configuration registers description Bit # Name CR0 (offset = 00h), LID - Loaded identification number of device and vendor 31~16 LDID 15~0 LVID From EEPROM: Loaded from EEPROM CR1 (offset = 04h), CSC - Configuration command and status ...
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... CSE 7 --- 6 CPE 5~ 3 --- 2 CMO 1 CMSA 0 CIOSA R/W: Read and write able. RO: Read able only. CR2 (offset = 08h Class code and revision number 31~24 BCC 23~16 SC 15~ 8 --- RO: Read only Registers and descriptors description Description New capabilities. Indicates whether the STE10/100A provides a list of extended capabilities, such as PCI power management ...
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... IOSI CR11 (offset = 2ch), SID - Subsystem ID 31~16 SID 15~ 0 SVID CR12 (offset = 30h), BRBA - Boot ROM base address. This register should be initialized before accessing the boot ROM space. 34/82 Description Reserved Latency timer. This value specifies the latency timer of the STE10/100A in units of PCI bus clock cycles. ...
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... ROM. Reserved Boot ROM enable. The STE10/100A will only enable its boot ROM access if both the memory space access bit (bit 1 of CR1) and this bit are set enable boot ROM. (If bit 1 of CR1 is also set). Reserved Capabilities pointer Max_Lat register ...
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... Power management state. Aux current. These three bits report the maximum 3.3Vaux current requirements for STE10/100A chip. If bit 31 of PMR0 is ‘1’, the default value is 111b, meaning the STE10/100A needs 375 mA to support remote wake-up in D3cold power state. Otherwise, the default value is 000b, meaning the STE10/100A does not support remote wake-up from D3cold power state ...
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... PME_En. When set, enables the STE10/100A to assert PME#. When cleared, disables the PME# assertion. If PSD3c (bit 31 of PMR0) is cleared (i.e. it does not support PME# generation from D3cold), this bit is by default 0; otherwise, PME_En is cleared upon power up reset only and is not modified by either hardware or software reset ...
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... The definition of this field is given below. 00b - D0 01b - D1 10b - D2 11b - D3hot If software attempts to write an unsupported state to this field, the write operation will complete normally on the bus, but the data is discarded and no state change occurs. STE10/100A Default RW type 000000b RO 00b ...
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... CSR23 TXBR Transmit burst counter/time-out register CSR24 FROM Flash(boot) ROM port CSR25 PAR0 Physical address register 0 CSR26 PAR1 Physical address register 1 CSR27 MAR0 Multicast address hash table register 0 CSR28 MAR1 Multicast address hash table register 1 Registers and descriptors description Descriptions 39/82 ...
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... Reserved Cache alignment. Address boundary for data burst, set after reset 00: reserved (default) 01 boundary alignment 10 boundary alignment 11 boundary alignment Programmable burst length. This value defines the maximum number transferred in one DMA transaction. Value: 0 (unlimited (default), 32 STE10/100A Default RW type 0 R/W* 0 R/W* 0 R/W* ...
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... TPDM R/W* = Before writing the transmit process should be in the suspended state CSR2 (offset = 10h), RDR - Receive demand register RPDM R/W* = Before writing the receive process should be in the suspended state CSR3 (offset = 18h), RDB - Receive descriptor base address 31~ 2 SAR 1, 0 ...
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... RS 16 NISS 42/82 Description Reserved Bus error type. This field is valid only when bit 13 of CSR5(fatal bus error) is set. There is no interrupt generated by this field. 000: parity error, 001: master abort, 010: target abort 011, 1xx: reserved Transmit state. Reports the current transmission state only, no interrupt will be generated ...
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... Receive watchdog timeout, based on CSR15 watchdog timer register Receive process stopped, receive state = stop Receive descriptor unavailable. 1: when the next receive descriptor can not be obtained by the STE10/100A. The receive process is suspended in this situation. To restart the receive process, the ownership bit of the next ...
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... Transmit process stopped. 1: while transmit state = stop Transmit completed interrupt. 1: set when a frame transmission completes with IC (bit 31 of TDES1) asserted in the first transmit descriptor of the frame. Reserved Store and forward for transmit 0: disable 1: enable, ignore the transmit threshold setting ...
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... SR 0 --- W* = only write when the transmit processor stopped. W** = only write when the transmit and receive processor both stopped. W*** = only write when the receive processor stopped. Registers and descriptors description Description Force collision mode 0: disable 1: generate collision upon transmit (for testing in ...
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... TJTTIE 46/82 Description Reserved Normal interrupt enable. 1: enables all the normal interrupt bits (see bit 16 of CSR5). Abnormal interrupt enable. 1: enables all the abnormal interrupt bits (see bit 15 of CSR5). Reserved Fatal bus error interrupt enable. 1: this bit in conjunction with AIE (bit 15 of CSR7) will enable the fatal bus error interrupt ...
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... NIE (bit 16 of CSR7) will enable the transmit descriptor unavailable interrupt. Transmit processor stopped interrupt enable. 1: this bit in conjunction with AIE (bit 15 of CSR7) will enable the transmit processor stopped interrupt. Transmit completed interrupt enable. 1: this bit in conjunction with NIE (bit 16 of CSR7) will enable the transmit completed interrupt ...
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... Wake-up pattern five matched enable Reserved Link off detect enable. The STE10/100A will set the LSC bit of CSR13 after it has detected that link status has switched from ON to OFF. Link on detect enable. The STE10/100A will set the LSC bit of CSR13 after it has detected that link status has switched from OFF to ON ...
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... It is cleared by writing upon power-up reset not affected by a hardware or software reset. Magic packet received, 1: Indicates STE10/100A has received a magic packet cleared by writing upon power- up reset not affected by a hardware or software reset. Link status changed, 1: Indicates STE10/100A has detected a link status change event cleared by writing upon power-up reset ...
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... Offset value is from 0-255 (8-bit width). To load the whole wake-up frame filtering information, consecutive 25 long words write operation to CSR14 should be done. CSR15 (offset = 78h), WTMR - Watchdog timer 31~6 --- 5 RWR 4 RWD 3 --- ...
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... STE10/100A Table 8. Control/status register description (continued) Bit # Name 2 JCLK JBD CSR16 (offset = 80h), ACSR5 - Assistant CSR5 (Status register 2) 31 TEIS 30 REIS 29 XIS 28 TDIS 27 --- 26 PFR 25~ 23 BET Registers and descriptors description Description Jabber clock 0: cut off transmission after 2.6 ms (100Mbps (10Mbps). ...
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... Registers and descriptors description Table 8. Control/status register description (continued) Bit # Name 22 19~ ANISS 15 AAISS 14~0 LH* = High Latching and cleared by writing 1 CSR17 (offset = 84h), ACSR7- Assistant CSR7 (Interrupt enable register 2) 31 TEIE 30 REIE 29 XIE 28 TDIE 27 --- 26 PFRIE 25~17 --- 52/82 Description Transmit state. Reports the current transmission state only, no interrupt will be generated ...
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... STE10/100A Table 8. Control/status register description (continued) Bit # Name 16 ANISE 15 AAIE 14~0 CSR18 (offset = 88h Command register bit31 to bit16 automatically recall from EEPROM 31 D3CS 30-28 AUXCL 27-24 --- 4LEDmod 23 e_on 22, 21 RFS 20 --- Registers and descriptors description Description Added normal interrupt summary enable. 1: adds the interrupts of bits 30 and 31 of ACSR7 (CSR17) to the normal interrupt summary (bit 16 of CSR5) ...
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... STE10/100A will set the Cap_Ptr register to zero, indicating no PCI compliant power management capabilities. The value of this bit will be mapped to NC (CR1 bit 20). In PCI power management mode, the wake up frames include “Magic Packet”, “Unicast”, and “ ...
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... PME_Status. This bit is set whenever the STE10/100A detects a wake-up event, regardless of the state of the PME-En bit. Writing a “1” to this bit will clear it, causing the STE10/100A to deassert PME# (if so enabled). Writing a “0” has no effect. Data_Scale. Indicates the scaling factor to be used when interpreting the value of the data register ...
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... Control/status register description (continued) Bit # Name 1,0 PWRS CSR23 (offset = 9ch), TXBR - Transmit burst count / time-out 31~21 --- 20~16 TBCNT 15~12 --- 11~0 TTO CSR24 (offset = a0h), FROM - Flash ROM (also the boot ROM) port 31 bra16_on 30~28 --- 27 REN 26 WEN 25 --- 24~8 ADDR 7~0 DATA ...
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... PAB5 7~0 PAB4 For example, physical address = 00-00-e8-11-22-33 - PAR0 PAR1 PAR0 and PAR1 are readable, but can be written only if the receive state is in stopped (CSR5 bits 19-17=000). CSR27 (offset = ach), MAR0 - Multicast address register 0 31~24 MAB3 23~16 MAB2 ...
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... Mb/s auto-negotiation on twisted pair” of the IEEE802.3u standard. In addition, 4 special registers are provided for advanced chip control and status. Note: Since only double word access is supported for register R/W in the STE10/100A, the higher word (bit 31~16) of the XCVR registers (XR0~XR10) should be ignored. Table 9. ...
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... RSAN 8 DPSEL 7 COLEN 6~0 --- R/W = Read/Write able Read only. XR1(offset = b8h) - XSR, XCVR status register. All the bits of this register are read only TXFD 13 TXHD Registers and descriptors description Description Transceiver reset control. 1: reset transceiver. This bit will be cleared by STE10/100A after transceiver reset has completed ...
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... ANC LINK 1 JAB 0 EXT LL* = Latching Low and clear by read. LH* = Latching High and clear by read. XR2(offset = bch) - PID1, PHY identifier 1 15~0 PHYID1 XR3(offset = c0h) - PID2, PHY identifier 2 15~10 PHYID2 9~4 MODEL 3~0 REV 60/82 Description 10BASE-T full duplex ability. Always 1, since STE10/100A has 10Base-T full duplex ability ...
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... STE10/100A’s link code word. Link partner’s remote fault status remote fault detected. 1: remote fault detected. Reserved Link partner’s flow control ability. 0: link partner without PAUSE function ability. 1, link partner with PAUSE function ability for full duplex link. Default RW type ...
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... Link partner select field. Standard IEEE 802.3 = 00001 reserved Parallel detection fault fault detected fault detected via parallel detection function. Link partner’s next page ability. 0: link partner without next page ability. 1: link partner with next page ability. STE10/100A’s next page ability. ...
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... STE10/100A Table 10. Transceiver registers description (continued) Bit # Name XR7(offset = d0h) - XMC, XCVR mode control 15~12 --- 11 LD 10~0 --- XR8(offset = d4h) - XCIIS, XCVR configuration information and interrupt status 15~10 ---- 9 SPEED 8 DUPLEX 7 PAUSE 6 ANC 5 RFD ANAR 2 PDF 1 ANPR Registers and descriptors description Description Reserved Long distance mode of 10BASE-T ...
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... DISRER 12 ANC 64/82 Description Receive error full interrupt. 0: the receive error number is less than 64 error packets is received. Reserved Auto-negotiation completed interrupt enable. 0: disable auto-negotiation completed interrupt. 1: enable auto-negotiation complete interrupt. Remote fault detected interrupt enable. 0: disable remote fault detection interrupt. ...
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... DC restoration. Enable the conversions between NRZ and NRZI. 0: disable the data conversion between NRZ and NRZI. 1: enable the data conversion of NRZI to NRZ in receiving and NRZ to NRZI in transmitting. Reserved Transmit Isolation. When 1, isolate from MII and tx+/-. This bit must be 0 for normal operation Reports current transceiver operating mode ...
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... Transceiver loop-back 11: remote loop-back These bits are valid only in a frame’s last descriptor. Runt frame (packet length < 64 bytes). This bit is valid only in a frame’s last descriptor. Multicast frame. This bit is valid only in a frame’s last descriptor. STE10/100A ...
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... Packet too long (packet length > 1518 bytes). This bit is valid only in a frame’s last descriptor. Late collision. Set when collision is active after 64 bytes. This bit is valid only in a frame’s last descriptor Frame type. This bit is valid only in a frame’s last descriptor. ...
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... Buffer2 address Description Own bit 1: Indicates this descriptor is ready to transmit 0: No transmit data in this descriptor. Reserved Under-run count Reserved Error summary. Logical OR of the following bits: 1: under-run error 8: excessive collision 9: late collision 10: no carrier 11: loss carrier 14: jabber time-out Transmit jabber time-out ...
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... Registers and descriptors description Description First descriptor Reserved Disable add CRC function End of ring 2nd address chain. Indicates that the buffer 2 address is the next descriptor address Disable padding function Reserved Buffer 2 size Buffer 1 size Buffer address 1. No alignment limitations imposed on the transmission buffer address ...
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... Enable flow control function. PCI device ID PCI vendor ID PCI subsystem ID PCI subsystem vendor ID MIN_GNT value MAX_LAT value Cardbus CIS pointer CSR18 (CR) bit 31-16 recall data Reserved, should be zero CheckSum, the least significant two bytes of FCS for data stored in offset 0..7D of EEPROM STE10/100A , ...
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... Name 0xFFFF 0x0100 0x0200 0x0400 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0010 0x0013 0x0015 General EEPROM format description Description Software driver default Auto-negotiation Power-on auto-detection Auto sense 10BaseT BNC AUI 100BaseTx 100BaseT4 100BaseFx 10BaseT full duplex 100BaseTx full duplex 100BaseFx full duplex ...
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... Electrical specifications and timings 6 Electrical specifications and timings Table 17. Absolute maximum ratings Parameter Supply voltage(Vcc) Input voltage Output voltage Storage temperature Ambient temperature ESD protection Table 18. General DC specifications Symbol General DC Vcc Supply voltage Icc Power supply PCI interface DC specifications Vilp Input LOW voltage ...
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... Input differential reject peak Vidr100 voltage Output differential peak Vod100 voltage Table 19. AC specifications Symbol PCI signaling AC specifications Ioh(AC) Switching current high Iol(AC) Switching current low Icl Low clamp current Tr Unloaded output rise time Tf Unloaded output fall time 6.1 Timing specifications Table 20 ...
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... Tval(ptp) (point to point) Ton Float to active delay Toff Active to float delay Input set up time to clock Tsu (bussed signals) Input set up time to clock Tsu(ptp) (point to point) Th Input hold time from clock Th Input hold time from clock Reset active time after power Trst ...
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... Figure 17. PCI timings INPUT Table 23. Flash interface timings Symbol Tfcyc Read/write cycle time Address to read data setup Tfce time Tfce CS# to read data setup time OE# active to read data Tfoe setup time OE# inactive to data driven Tfdf delay time Address setup time before Tfas WE# Tfah ...
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... Figure 19. Flash read timings ADDRESS Table 24. EEPROM Interface Timings Symbol Tscf Serial clock frequency Delay from CS high to SK Tecss high Tecsh Delay from SK low to CS low Tedts Setup time Tedth Hold time of DI after SK Tecsl CS low time 76/82 Tfcyc Tahw Tfasw ...
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... STE10/100A Figure 20. Serial EEPROM timings CS CLK DI Table 25. 10BASE-T normal link pulse (NLP) timings specifications Symbol Tnpw NLP width Tnpc NLP period Figure 21. Normal link pulse timings Table 26. Auto-negotiation fast link pulse (FLP) timings specifications Symbol Tflpw FLP Width Clock pulse to clock pulse ...
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... Electrical specifications and timings Figure 22. Fast link pulse timings Table 27. 100BASE-TX transmitter AC timings specification Symbol TDP-TDN differential output Tjit peak jitter 78/82 Tflcpp Tflcpd Tflpw Tflbp Tflbw Parameter Test condition STE10/100A Min. Typ. Max. Units 1.4 ps ...
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... In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK trademark. ...
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... C 0. 0.5 HD 23.2 HE 17.2 L 0.73 0.88 L1 1.60 ZD 0.75 ZE 0.75 ccc Angle L dimension is measured at gauge plane at 0.25 above the seating plane ZD 102 103 b PIN 1 ID 128 1 e May 1999 80/82 inch MAX. MIN. TYP. MAX. 3.40 0.12 0.134 0.010 0.013 2.87 0.101 ...
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... STE10/100A 8 Ordering information Table 28. Order codes Part number E-STE10/100A 9 Revision history Table 29. Document revision history Date 06-Nov-2002 28-Feb-2007 PQFP128 (14mm x 20mm x 2.7mm) Revision 7 Previous release (as revision A07) Removed the STE10/100E order code and updated the ordering 8 information. Ordering information Package Changes ...
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