LAN91C100FDTQFP SMSC, LAN91C100FDTQFP Datasheet - Page 61

• Manufacturer Part Number: LAN91C100FDTQFP
• Description: Ethernet ICs Non-PCI 10/100 Ethernet MAC
• Manufacturer: SMSC
• Type: Single Chip MAC and PHY Controllerr

Specifications of LAN91C100FDTQFP

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: 802.3
• Data Rate: 10 Mbps, 100 Mbps
• Supply Voltage (max): 7 V
• Supply Voltage (min): 0.3 V
• Supply Current (max): 40 mA
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFP-208
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SMSC LAN91C100FD Rev. D
FEAST Fast Ethernet Controller with Full Duplex Capability
additional logic)
EISA BUS
nDAK<n>
nEXRDY
SIGNAL
(optional
nNOWS
nIOWC
nEX32
nIORC
BCLK
GND
VCC
THE FOLLOWING SIGNALS SUPPORT SLAVE DMA TYPE "C" BURST CYCLES
LAN91C100FD
nRDYRTN
nDATACS
nCYCLE
SIGNAL
nVLBUS
nLDEV
LCLK
W/nR
A1
nLDEV is a totem pole output. nLDEV is active on valid
decodes of LAN91C100FD pins A15-A4, and AEN=0.
nNOWS is similar to nLDEV except that it should go inactive
on nSTART rising. nNOWS can be used to request
compressed cycles (1.5 BCLK long, nRD/nWR will be 1/2
BCLK wide).
EISA Bus Clock. Data transfer clock for DMA bursts.
DMA Acknowledge. Active during Slave DMA cycles. Used
by the LAN91C100FD as nDATACS direct access to data
path.
Indicates the direction and timing of the DMA cycles. High
during LAN91C100FD writes, low during LAN91C100FD
reads.
Indicates slave DMA writes.
EISA bus signal indicating whether a slave DMA cycle will
take place on the next BCLK rising edge, or should be
postponed. nRDYRTN is used as an input in the slave DMA
mode to bring in EXRDY.
DATASHEET
UNUSED PINS
Page 61
NOTES
Revision 1.0 (09-22-08)