LAN9118-MD SMSC, LAN9118-MD Datasheet
LAN9118-MD
Specifications of LAN9118-MD
Related parts for LAN9118-MD
LAN9118-MD Summary of contents
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... Easily interfaces to most 32-bit and 16-bit embedded CPU’s Integrated PHY Supports audio & video streaming over Ethernet: multiple high-definition (HD) MPEG2 streams Pin compatible with other members of LAN9118 family (LAN9117, LAN9116 and LAN9115) Target Applications Video distribution systems, multi-room PVR High-end Cable, satellite, and IP set-top boxes ...
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... LAN9118-MT FOR 100 PIN, TQFP LEAD-FREE ROHS COMPLIANT PACKAGE WITH E3 FINISH 80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123 Copyright © 2008 SMSC or its subsidiaries. All rights reserved. Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given ...
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... Hardware Reset Input (nRESET 3.11.3 Resume Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.11.4 Soft Reset (SRST 3.11.5 PHY Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.12 TX Data Path Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.12.1 TX Buffer Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.12.2 TX Command Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.12.3 TX Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.12.4 TX Status Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.12.5 Calculating Actual TX Data FIFO Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 SMSC LAN9118 3 DATASHEET Revision 1.5 (07-11-08) ...
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... BYTE_TEST—Byte Order Test Register 5.3.6 FIFO_INT—FIFO Level Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 5.3.7 RX_CFG—Receive Configuration Register 5.3.8 TX_CFG—Transmit Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 5.3.9 HW_CFG—Hardware Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 5.3.10 RX_DP_CTRL—Receive Datapath Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Revision 1.5 (07-11-08) High Performance Single-Chip 10/100 Non-PCI Ethernet Controller 4 DATASHEET Datasheet SMSC LAN9118 ...
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... PIO Burst Reads 118 6.4 RX Data FIFO Direct PIO Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 6.5 RX Data FIFO Direct PIO Burst Reads 120 6.6 PIO Writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 6.7 TX Data FIFO Direct PIO Writes 122 6.8 Reset Timing 123 6.9 EEPROM Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 SMSC LAN9118 5 DATASHEET Revision 1.5 (07-11-08) ...
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... Power Consumption Device Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 7.4 Power Consumption Device and System Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 7.5 DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 7.6 Clock Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Chapter 8 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Chapter 9 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Revision 1.5 (07-11-08) High Performance Single-Chip 10/100 Non-PCI Ethernet Controller 6 DATASHEET Datasheet SMSC LAN9118 ...
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... High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet List of Figures Figure 1.1 System Block Diagram Utilizing the SMSC LAN9118 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 1.2 Internal Block Diagram Figure 2.1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 3.1 VLAN Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 3.2 VLAN Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 3.3 EEPROM Access Flow Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 3 ...
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... Table 5.5 Backpressure Duration Bit Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Table 5.6 LAN9118 MAC CSR Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Table 5.7 ADDRL, ADDRH and EEPROM Byte Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Table 5.8 LAN9118 PHY Control and Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Table 5.9 MODE Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Table 6.1 Read After Write Timing Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Table 6 ...
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... The LAN9118 also supports features which reduce or eliminate packet loss. Its internal 16-KByte SRAM can hold over 200 received packets. If the receive FIFO gets too full, the LAN9118 can automatically generate flow control packets to the remote node, or assert back-pressure on the remote node by generating network collisions ...
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... Figure 1.1 System Block Diagram Utilizing the SMSC LAN9118 The SMSC LAN9118 integrated 10/100 MAC/PHY controller is a peripheral chip that performs the function of translating parallel data from a host controller into Ethernet packets. The LAN9118 Ethernet MAC/PHY controller is designed and optimized to function in an embedded environment. All communication is performed with programmed I/O transactions using the simple SRAM-like host interface bus ...
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... GP Timer 1.2 10/100 Ethernet PHY The LAN9118 integrates an IEEE 802.3 physical layer for twisted pair Ethernet applications. The PHY can be configured for either 100 Mbps (100Base-TX Mbps (10Base-T) Ethernet operation in either full or half duplex configurations. The PHY block includes auto-negotiation. Minimal external components are required for the utilization of the Integrated PHY. ...
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... The GPIO’s (GPO’s are not configurable) can also be configured to trigger interrupts with programmable polarity. 1.7 Serial EEPROM Interface A serial EEPROM interface is included in the LAN9118. The serial EEPROM is optional and can be programmed with the LAN9118 MAC address. The LAN9118 can optionally load the MAC address automatically after power-on. 1.8 ...
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... The host bus data Interface is responsible for host address decoding and data bus steering. The host bus interface handles the 16 to 32-bit conversion when the LAN9118 is configured with a 16-bit host interface. Additionally, when Big Endian mode is selected, the data path to the internal controller registers will be reorganized accordingly ...
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... High Performance Single-Chip 10/100 Non-PCI Ethernet Controller SMSC LAN9118 100 PIN TQFP Figure 2.1 Pin Configuration 14 DATASHEET Datasheet 50 D10 49 D11 48 VDD_IO 47 GND_IO 46 D12 45 D13 44 D14 43 D15 42 VDD_IO 41 GND_IO 40 D16 39 D17 38 D18 37 D19 36 D20 35 VDD_IO 34 GND_IO 33 D21 32 D22 31 D23 30 D24 29 D25 28 VDD_IO 27 GND_IO 26 D26 SMSC LAN9118 ...
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... LAN9118 when reduced power state. Programmable Interrupt request. Programmable polarity, source and buffer types. When driven high all accesses to the LAN9118 are to the Data FIFOs. In this mode, the A[7:3] upper address inputs are ignored. AUTO NEG. DISABLED ENABLED Revision 1.5 (07-11-08) ...
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... Data Bus Width Select: This signal also functions as a configuration input on power-up and is used to select the host bus data width. Upon deassertion of reset, the value of the input is latched. When high, a 32-bit data bus is utilized. When low, a 16- bit interface is utilized. Serial EEPROM chip select. SMSC LAN9118 ...
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... External 25MHz Crystal output. Active-low reset input. Resets all logic and registers within the LAN9118 This signal is pulled high with a weak internal pull-up resistor. If nRESET is left unconnected, the LAN9118 will rely on its internal power-on reset circuitry Note: The LAN9118 must always ...
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... Reserved 5 I (PU DATASHEET Datasheet DESCRIPTION When programmed to do so, is asserted when the LAN9118 detects a wake event and is requesting the system to wake up from the associated sleep state. The polarity and buffer type of this signal is programmable. Note: Detection of a Power Management Event, and ...
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... This signal is driven high only during 10Mbs operation. nLED2 (Link & Activity Indicator). This signal is driven low (LED on) when the LAN9118 detects a valid link. This signal is pulsed high (LED off) for 80mS whenever transmit or receive activity is detected. This signal is then driven low again for a ...
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... Reference Ground Note 2.1 Please refer to the SMSC application note AN 12.5 titled “Designing with the LAN9118 - Getting Started” also important to note that this application note applies to the whole SMSC LAN9118 family of Ethernet controllers. However, subtle differences may apply. Revision 1.5 (07-11-08) ...
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... OD8 Output 8mA symmetrical drive O8 50uA (typical) internal pull-up PU 50uA (typical) internal pull-down PD Analog input AI Analog output AO Analog bi-directional AIO Crystal oscillator input pin ICLK Crystal oscillator output pin OCLK SMSC LAN9118 Table 2.6 Buffer Types DESCRIPTION 21 DATASHEET Revision 1.5 (07-11-08) ...
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... Generation of control frames Interface to the internal PHYl The transmit and receive data paths are separate within the LAN9118 from the MAC to host interface allowing the highest performance, especially in full duplex mode. Payload data as well as transmit and receive status are passed on these busses. ...
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... High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 3.2 Flow Control The LAN9118 Ethernet MAC supports full-duplex flow control using the pause operation and control frame. It also supports half-duplex flow control using back pressure. 3.2.1 Full-Duplex Flow Control The pause operation inhibits data transmission of data frames for a specified period of time. A Pause ...
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... High Performance Single-Chip 10/100 Non-PCI Ethernet Controller VLAN 2 CCC DDD EEE LAN Switch #1 VLAN Config Data VLAN # AAA VLAN 3 BBB VLAN 3 CCC VLAN 3 DDD VLAN 2 EEE VLAN 2 FFF VLAN 2 GGG VLAN 1 HHH VLAN 1 Figure 3.1 VLAN Topology 24 DATASHEET Datasheet VLAN 1 FFF GGG HHH LAN Switch #3 SMSC LAN9118 ...
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... Upon recognizing that a frame has a VLAN tag, counter thresholds are adjusted to account for the extra bytes that the VLAN tag adds to the frame. The maximum length of the good packet is thus changed from 1518 bytes to 1522 bytes. SMSC LAN9118 Figure 3.2 VLAN Frame 25 DATASHEET Revision 1 ...
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... The first bit of the destination address signifies whether physical address or a multicast address. The LAN9118 address check logic filters the frame based on the Ethernet receive filter mode that has been enabled. Filter modes are specified based on the state of the control bits in Filtering Modes" ...
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... Hash Perfect Filtering In hash perfect filtering, if the received frame is a physical address, the LAN9118 Packet Filter block perfect-filters the incoming frame’s destination field with the value programmed into the MAC Address High register and the MAC Address Low register. If the incoming frame is a multicast frame, however, the LAN9118 packet filter function performs an imperfect address filtering against the hash table ...
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... FILTER I BYTE MASK DESCRIPTION Table 3.4 FILTER i COMMANDS Table 3.5 describes the Filter i Offset bit fields. 28 DATASHEET Datasheet WUCSR—Wake-up MAC_CR—MAC Control Filter 1 Reserved Filter 0 Command Filter 0 Offset Filter 0 CRC-16 Filter 2 CRC-16 shows the Filter I command register. SMSC LAN9118 ...
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... MAC examines receive data for a Magic Packet. The LAN9118 can be programmed to notify the host of the “Magic Packet” detection with the assertion of the host interrupt (IRQ) or assertion of the power managment event signal (PME). Upon detection, the Magic Packet Received bit (MPR) in the WUCSR is set ...
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... This is not a fatal error. The LAN9118 will reset its read counters and restart a new cycle on the next read. The Upper 16 data pins (D[31:16]) are not driven by the LAN9118 in 16-bit mode. These pins have internal pull-down’s and the signals are left in a high-impedance state ...
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... Endianess does not matter when both WORD lanes are in operation” is true for the LAN9118 device. However all designs important for the PCB layout designer to route the signal byte lanes appropriately relative to the processor type (Big vs. Little Endian). ...
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... Note: The EEPROM device powers-up in the erase/write disabled state. To modify the contents of the EEPROM the host must first issue the EWEN command operation is attempted, and an EEPROM device does not respond within 30mS, the LAN9118 will timeout, and the EPC timeout bit (EPC_TO) in the E2P_CMD register will be set. ...
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... E2P_CMD field settings for each command. ERASE (Erase Location): If erase/write operations are enabled in the EEPROM, this command will erase the location selected by the EPC Address field (EPC_ADDR). The EPC_TO bit is set if the EEPROM does not respond within 30ms. SMSC LAN9118 EEPROM Read Idle Write Data ...
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... EEPROM.The EPC_TO bit is set if the EEPROM does not respond within 30ms. EECS EECLK EEDIO (OUTPUT EEDIO (INPUT) Revision 1.5 (07-11-08) High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Figure 3.4 EEPROM ERASE Cycle Figure 3.5 EEPROM ERAL Cycle 34 DATASHEET Datasheet t CSL t CSL SMSC LAN9118 ...
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... Disable” command is sent, or until power is cycled. Note: The EEPROM device will power-up in the erase/write-disabled state. Any erase or write operations will fail until an Erase/Write Enable command is issued. EECS EECLK EEDIO (OUTPUT) EEDIO (INPUT) SMSC LAN9118 Figure 3.6 EEPROM EWDS Cycle 1 ...
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... EPC Address field (EPC_ADDR). The EPC_TO bit is set if the EEPROM does not respond within 30ms. EECS EECLK EEDIO (OUTPUT EEDIO (INPUT) Revision 1.5 (07-11-08) High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Figure 3.8 EEPROM READ Cycle Figure 3.9 EEPROM WRITE Cycle 36 DATASHEET Datasheet t CSL CSL D0 SMSC LAN9118 ...
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... EEPROM Data Register," on page 93 Supported EEPROM operations are described in these sections. 3.9.2.4 EEPROM Timing Refer to Section 6.9, "EEPROM Timing," on page 124 SMSC LAN9118 Figure 3.10 EEPROM WRAL Cycle Cycles", shown below, shows the number of EECLK cycles required for Table 3 ...
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... A write to the BYTE_TEST register, regardless of whether a wake-up frame or Magic Packet was detected, will return LAN9118 to the D0 state and will reset the PM_MODE field to the D0 state. As noted above, the host is required to check the READY bit and verify that it is set before attempting any other reads or writes of the device ...
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... High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Note 3.8 The host must do only read accesses prior to the ready bit being set. Once the READY bit is set, the LAN9118 is ready to resume normal operation. At this time the WUPS field can be cleared. 3.10.2.2 D2 Sleep In this state, as shown in placed in a reduced power state ...
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... WUPS bits clearing the corresponding WOL_EN or ED_EN bit. After clearing the internal pme_interrupt signal, the PME_INT status bit may be cleared by writing a ‘1’ to this bit in the INT_STS register. It should be noted that the LAN9118 can generate a host interrupt regardless of the state of the PME_EN bit, or the external PME signal. ...
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... Note 3.11 After any PHY reset, the application must wait until the “Link Status” bit in the PHY’s “Basic Status Register” (PHY Reg. 1.2) is set before attempting to transmit or receive data. Note 3.12 After a POR, nRESET or SRST, the LAN9118 will automatically check for the presence of an external EEPROM. After any of these resets the application must verify that the EPC ...
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... Upon completion of the hardware reset, the READY bit in PMT_CTRL is set high. After the “READY” bit is set, the LAN9118 can be configured via its control registers. The nRESET signal is pulled-high internally by the LAN9118 and can be left unconnected if unused. If used, nRESET must be driven low for a minimum period as defined in APPLICATION NOTE: Under normal conditions, the READY bit in PMT_CTRL will be set (high -” ...
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... Burst length regardless of the actual packet length. When configured to do so, the LAN9118 will accept extra data at the end of the packet and will remove the extra padding before transmitting the packet. The LAN9118 automatically removes data up to the boundary specified in the Buffer End Alignment field specified in each TX command ...
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... Figure 3.12 Simplified Host TX Flow Diagram Revision 1.5 (07-11-08) High Performance Single-Chip 10/100 Non-PCI Ethernet Controller init Idle TX Status Available Read TX Status (optional) Check available FIFO space Write TX Command Write Start Padding (optional) Not Last Buffer Write Buffer 44 DATASHEET Datasheet SMSC LAN9118 ...
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... The following diagram illustrates the buffer format. Host Write Figure 3.13, "TX Buffer Format", shows the TX Buffer written into the LAN9118. It should be noted that not all of the data shown in this diagram is actually stored in the TX data FIFO. This must be taken into account when calculating the actual TX data FIFO usage. Please refer to " ...
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... DWORD’s were added to the end of the Buffer. A running count is also maintained in the LAN9118 of the cumulative buffer sizes for a given packet. This cumulative value is compared against the Packet Length field in the TX command ‘B’ word and if they do not correlate, the TXE flag is set ...
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... The first buffer of any transmit packet can be any length Middle buffers (i.e., those with First Segment = Last Segment = 0) must be greater than, or equal to 4 bytes in length The final buffer of any transmit packet can be any length SMSC LAN9118 Table 3.12 TX Command 'B' Format DESCRIPTION Table 3.13, "TX DATA Start Table 3 ...
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... DWORDs (2,036 bytes total). Any transmit packet that is so highly fragmented that it takes more space than this must be un-fragmented (by copying to a Driver-supplied buffer) before the transmit packet can be sent to the LAN9118. One approach to determine whether a packet is too fragmented is to calculate the actual amount of space that it will consume, and check it against 2,036 bytes ...
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... Start Offset” 17-Bytes of payload data 16-Byte “Buffer End Alignment” Figure 3.14, "TX Example 1" illustrates the TX command structure for this example, and also shows how data is passed to the TX data FIFO. SMSC LAN9118 DESCRIPTION 49 DATASHEET Revision 1.5 (07-11-08) ...
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... Payload 1B 0 10-Byte TX Command 'A' TX Command 'B' 10-Byte Data Start Offset Figure 3.14 TX Example 1 50 DATASHEET Datasheet TX Data FIFO TX Command 'A' TX Command 'B' 79-Byte Payload TX Command 'A' 15-Byte Payload TX Command 'A' 17-Byte Payload NOTE: Extra bytes betw een buff ers are not transmitted SMSC LAN9118 ...
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... Ethernet Controller 31 TX Command 'A' Buffer End Alignment = 0 Data Start Offset = 6 First Segment = 1 Last Segment = 1 Buffer Size =183 TX Command 'B' Packet Length = 183 SMSC LAN9118 0 TX Command 'A' TX Command 'B' 6-Byte Data Start Offset 183-Byte Payload Data 3B End Padding Figure 3.15 TX Example 2 51 DATASHEET ...
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... The offset may be changed in between RX packets, but it must not be changed during an RX packet read. The LAN9118 can be programmed to add padding at the end of a receive packet in the event that the end of the packet does not align with the host burst boundary. This feature is necessary when the LAN9118 is operating in a system that always performs multi-DWORD bursts ...
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... The host should perform the proper number of reads, as indicated by the packet length plus the start offset and the amount of optional padding added to the end of the frame, from the RX data FIFO. Last Packet Figure 3.16 Host Receive Routine Using Interrupts Last Packet Figure 3.17 Host Receive Routine with Polling SMSC LAN9118 init Idle RX Interrupt Read RX Status ...
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... FIFOs. When activated, the read and write pointers for the RX data and status FIFOs will be returned to their reset state. To perform a receiver dump, the LAN9118 receiver must be halted. Once the receiver stop completion is confirmed, the RX_DUMP bit can be set in the RX_CFG register. The RX_DUMP bit is cleared when the dump is complete ...
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... Runt Frame. When set, this bit indicates that frame was prematurely terminated before the collision window (64 bytes). Runt frames are passed on to the host only if the Pass Bad Frames bit MAC_CR Bit [16] is set. 10 Multicast Frame. When set, this bit indicates that the received frame has a Multicast address. SMSC LAN9118 31 0 Optional offset DWORD0 . ...
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... Error (RXE) will be asserted under the following conditions: A host underrun of RX data FIFO A host underrun of the RX status FIFO An overrun of the RX status FIFO It is the duty of the host to identify and resolve any error conditions. Revision 1.5 (07-11-08) High Performance Single-Chip 10/100 Non-PCI Ethernet Controller DESCRIPTION 56 DATASHEET Datasheet SMSC LAN9118 ...
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... F. The remaining code-groups are given letter designations with slashes on either side. For example, an IDLE code-group is /I/, a transmit error code-group is /H/, etc. The encoding process may be bypassed by clearing bit 6 of register 31. When the encoding is th bypassed the 5 transmit data bit is equivalent to TX_ER. SMSC LAN9118 100M PLL 4B/5B 25MHz MII ...
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... Sent for falling TX_EN Sent for falling TX_EN Sent for rising TX_ER INVALID INVALID INVALID INVALID INVALID INVALID INVALID 58 DATASHEET Datasheet TRANSMITTER INTERPRETATION 0 0000 DATA 1 0001 2 0010 3 0011 4 0100 5 0101 6 0110 7 0111 8 1000 9 1001 A 1010 B 1011 C 1100 D 1101 E 1110 F 1111 SMSC LAN9118 ...
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... Phase Lock Loop (PLL) The 100M PLL locks onto reference clock and generates the 125MHz clock used to drive the 125 MHz logic and the 100Base-Tx Transmitter. SMSC LAN9118 Table 4.1 4B/5B Code Table (continued) RECEIVER INTERPRETATION 59 ...
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... Decoder 125 Mbps Serial DSP: Timing MLT-3 recovery, Equalizer and BLW Correction RJ45 MLT-3 MLT-3 6 bit Data Figure 4.2 Receive Data Path Figure 4.2. Detailed descriptions are given below. 60 DATASHEET Datasheet Descrambler 25MHz by 5 bits and SIPO CAT-5 SMSC LAN9118 ...
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... The 4-bit wide data is sent to the TX10M block. The nibbles are converted to a 10Mbps serial NRZI data stream. The 10M PLL locks onto the external clock or internal oscillator and produces a 20MHz clock. This is used to Manchester encode the NRZ data stream. When no data is being transmitted SMSC LAN9118 61 DATASHEET ...
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... Auto-negotiation is a mechanism for exchanging configuration information between two link-partners and automatically selecting the highest performance mode of operation supported by both sides. Auto-negotiation is fully defined in clause 28 of the IEEE 802.3 specification. Revision 1.5 (07-11-08) High Performance Single-Chip 10/100 Non-PCI Ethernet Controller 62 DATASHEET Datasheet SMSC LAN9118 ...
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... Auto-negotiation will also re-start if not all of the required FLP bursts are received. Writing register 4 bits [8:5] allows software control of the capabilities advertised by the PHY. Writing register 4 does not automatically re-start auto-negotiation. Register 0, bit 9 must be set before the new SMSC LAN9118 63 DATASHEET ...
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... Parallel Detection If the LAN9118 is connected to a device lacking the ability to auto-negotiate (i.e. no FLPs are detected able to determine the speed of the link based on either 100M MLT-3 symbols or 10M Normal Link Pulses. In this case the link is presumed to be half-duplex per the IEEE standard. This ability is known as “ ...
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... Mbps Note 4.1 The LAN9118 10/100 PHY CRS signal operates in two modes: Active and Low. When in Active mode, CRS will transition high and low upon line activity, where a high value indicates a carrier has been detected. In Low mode, CRS stays low and does not indicate carrier detection ...
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... Chapter 5 Register Description The following section describes all LAN9118 registers and data ports. FCh B4h B0h ACh A8h A4h A0h 50h 4Ch 48h 44h 40h 3Ch 24h 20h 1Ch 04h Base + 00h Revision 1.5 (07-11-08) High Performance Single-Chip 10/100 Non-PCI Ethernet Controller ...
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... LAN9118 registers accordingly. 5.2 RX and TX FIFO Ports The LAN9118 contains four host-accessible FIFOs: the RX Status, RX data, TX Status, and TX data FIFOs. The sizes of the RX and TX data FIFOs, as well as the RX Status FIFO are configurable through the CSRs. ...
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... The host may write to any of the 8(16) locations since they all access the same TX data FIFO location and perform the same function. 5.3 System Control and Status Registers Table 5.1, "LAN9118 Direct Address Register the host bus. Table 5.1 LAN9118 Direct Address Register Map BASE ADDRESS + OFFSET SYMBOL 50h ID_REV ...
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... High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Table 5.1 LAN9118 Direct Address Register Map (continued) BASE ADDRESS + OFFSET SYMBOL 9Ch FREE_RUN A0h RX_DROP A4h MAC_CSR_CMD A8h MAC_CSR_DATA ACh AFC_CFG B0h E2P_CMD B4h E2P_DATA B8h - FCh RESERVED 5.3.1 ID_REV—Chip ID and Revision Offset: This register contains the ID and Revision fields for this design ...
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... When set, the IRQ output is a Push-Pull driver. When configured as an open-drain output the IRQ_POL field is ignored, and the interrupt output is always active low. Revision 1.5 (07-11-08) High Performance Single-Chip 10/100 Non-PCI Ethernet Controller 54h Size: 70 DATASHEET Datasheet 32 bits TYPE DEFAULT R R R/W 0 NASR RO - R/W 0 NASR SMSC LAN9118 ...
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... PME hardware signal. Notes: Detection of a Power Management Event, and assertion of the PME signal will not wakeup the LAN9118. The LAN9118 will only wake up when it detects a host write cycle of any data to the BYTE_TEST register. ...
Page 72
... GPIO [2:0] (GPIOx_INT). Interrupts are generated from the GPIO’s. These interrupts are configured through the GPIO_CFG register. Revision 1.5 (07-11-08) High Performance Single-Chip 10/100 Non-PCI Ethernet Controller DESCRIPTION 72 DATASHEET Datasheet TYPE DEFAULT RO - R/WC 0 R/WC 0 R/WC 0 R/ R/WC 0 R/WC 0 R/WC 000 SMSC LAN9118 ...
Page 73
... TX Status FIFO Full Interrupt (TSFF_INT_EN Status FIFO Level Interrupt (TSFL_INT_EN Dropped Frame Interrupt Enable (RXDF_INT_EN) 5 Reserved 4 RX Status FIFO Full Interrupt (RSFF_INT_EN Status FIFO Level Interrupt (RSFL_INT_EN) 2-0 GPIO [2:0] (GPIOx_INT_EN). SMSC LAN9118 5Ch Size: 73 DATASHEET 32 bits TYPE DEFAULT R R/W 0 ...
Page 74
... When the RX Status FIFO used space is greater than this value an RX Status FIFO Level interrupt (RSFL) will be generated. Revision 1.5 (07-11-08) High Performance Single-Chip 10/100 Non-PCI Ethernet Controller 64h Size: 68h Size: 74 DATASHEET Datasheet 32 bits TYPE DEFAULT RO 87654321h 32 bits TYPE DEFAULT R/W 48h R/W 00h RO - R/W 00h SMSC LAN9118 ...
Page 75
... BITS 31:30 RX End Alignment. This field specifies the alignment that must be maintained on the last data transfer of a buffer. The LAN9118 will add extra DWORDs of data up to the alignment specified in the table below. The host is responsible for removing these extra DWORDs. This mechanism can be used to maintain cache line alignment on host processors ...
Page 76
... TX_CFG—Transmit Configuration Register Offset: This register controls the transmit functions on the LAN9118 Ethernet Controller. BITS DESCRIPTION 31-16 Reserved. 15 Force TX Status Discard (TXS_DUMP). This self-clearing bit clears the TX status FIFO of all pending status DWORD’s. When a ‘1’ is written, the TX status pointers are cleared to zero ...
Page 77
... The internal RX_CLK and TX_CLK signals must be running for a proper software reset. Please refer to Section 6.8, "Reset Timing," on page 123 The LAN9118 must always be read at least once after power-up, reset, or upon return from a power-saving state or write operations will not function. 5.3.9.1 Allowable settings for Configurable FIFO Memory Allocation TX and RX FIFO space is configurable through the CSR - HW_CFG register defined above ...
Page 78
... DATASHEET Datasheet RX STATUS FIFO SIZE (BYTES) 13440 896 12480 832 11520 768 10560 704 9600 640 8640 576 7680 512 6720 448 5760 384 4800 320 3840 256 2880 192 1920 128 SMSC LAN9118 ...
Page 79
... Depending on the size of the frames to be transmitted, the MIL can hold up to two Ethernet frames. This is in addition to any TX data that may be queued in the TX data FIFO. Conversely, as data is received by the LAN9118 moved from the MAC to the RX MIL FIFO, and then into the RX data FIFO. When the RX data FIFO fills up, data will continue to collect in the RX MIL FIFO ...
Page 80
... RX_FFWD. 30-0 Reserved 5.3.11 RX_FIFO_INF—Receive FIFO Information Register Offset: This register contains the used space in the receive FIFOs of the LAN9118 Ethernet Controller. BITS DESCRIPTION 31-24 Reserved 23-16 RX Status FIFO Used Space (RXSUSED). Indicates the amount of space in DWORDs, used in the RX Status FIFO ...
Page 81
... High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 5.3.12 TX_FIFO_INF—Transmit FIFO Information Register Offset: This register contains the free space in the transmit data FIFO and the used space in the transmit status FIFO in the LAN9118. BITS DESCRIPTION 31-24 Reserved 23-16 TX Status FIFO Used Space (TXSUSED). Indicates the amount of space in DWORDS used in the TX Status FIFO ...
Page 82
... Offset: This register controls the Power Management features. This register can be read while the power saving mode. LAN9118 Note: The LAN9118 must always be read at least once after power-up, reset, or upon return from a power-saving state or write operations will not function. BITS DESCRIPTION ...
Page 83
... Device Ready (READY). When set, this bit indicates that LAN9118 is ready to be accessed. This register can be read when LAN9118 is in any power management mode. Upon waking from any power management mode, including power-up, the host processor can interrogate this field as an indication when LAN9118 has stabilized and is fully alive ...
Page 84
... GPIO2 – bit 10 7:5 Reserved Revision 1.5 (07-11-08) High Performance Single-Chip 10/100 Non-PCI Ethernet Controller 88h Size: Description for the EEPROM Enable bit function definitions. 84 DATASHEET Datasheet 32 bits Type Default RO - R/W 000 RO - R/W 000 RO - R/W 000 RO - R/W 000 RO - R/W 0000 RO - SMSC LAN9118 ...
Page 85
... Timer is put into the run state. When cleared, the GP Timer is halted. On the transition of this bit the GPT_LOAD field will be preset to FFFFh. 28-16 Reserved 15-0 General Purpose Timer Pre-Load (GPT_LOAD). This value is pre-loaded into the GP-Timer. SMSC LAN9118 Description EEDIO FUNCTION EEDIO GPO3 Reserved GPO3 ...
Page 86
... This register controls how words from the host data bus are mapped to the CRSs and Data FIFOs inside the LAN9118. The LAN9118 always sends data from the Transmit Data FIFO to the network so that the low order word is sent first, and always receives data from the network to the Receive Data FIFO so that the low order word is received first ...
Page 87
... DESCRIPTION 31-0 RX Dropped Frame Counter (RX_DFC). This counter is incremented every time a receive frame is dropped. RX_DFC is cleared on any read of this register. An interrupt can be issued when this counter passes through its halfway point (7FFFFFFFh to 80000000h). SMSC LAN9118 9Ch Size: A0h Size: 87 DATASHEET 32 bits ...
Page 88
... MAC CSR Data. Value read from or written to the MAC CSR’s. Revision 1.5 (07-11-08) High Performance Single-Chip 10/100 Non-PCI Ethernet Controller A4h Size: A8h Size: 88 DATASHEET Datasheet 32 bits TYPE DEFAULT R/W 00h 32 bits TYPE DEFAULT R/W 00000000h SMSC LAN9118 ...
Page 89
... AFC_CFG – Automatic Flow Control Configuration Register Offset: This register configures the mechanism that controls both the automatic, and software-initiated transmission of pause frames and back pressure. Note: The LAN9118 will not transmit pause frames or assert back pressure if the transmitter is disabled. BITS DESCRIPTION ...
Page 90
... BITS DESCRIPTION 0 Flow Control on Any Frame (FCANY). When this bit is set, the LAN9118 will assert back pressure, or transmit a pause frame when the AFC level is reached and any frame is received. Setting this bit enables full-duplex flow control when the LAN9118 is operating in full-duplex mode. ...
Page 91
... Note: EPC busy will be high immediately following power-up or reset. After the EEPROM controller has finished reading (or attempting to read) the MAC address from the EEPROM the EPC Busy bit is cleared. SMSC LAN9118 B0h Size: 91 DATASHEET 32 bits TYPE ...
Page 92
... MAC Address Reload operation will fail. The “MAC Address Loaded” bit indicates a successful load of the MAC address. 27-10 Reserved. Revision 1.5 (07-11-08) High Performance Single-Chip 10/100 Non-PCI Ethernet Controller [28] OPERATION 0 READ 1 EWDS 0 EWEN 1 WRITE 0 WRAL 1 ERASE 0 ERAL 1 Reload 92 DATASHEET Datasheet TYPE DEFAULT R SMSC LAN9118 ...
Page 93
... This register is used in conjunction with the E2P_CMD register to perform read and write operations with the Serial EEPROM BITS DESCRIPTION 31-8 Reserved. 7:0 EEPROM Data. Value read from or written to the EEPROM. SMSC LAN9118 When set, this bit indicates that a valid EEPROM B4h Size: 93 DATASHEET TYPE DEFAULT ...
Page 94
... MAC_CSR_CMD and MAC_CSR_DATA registers (see sections MAC_CSR_CMD – MAC CSR Synchronizer Command Register and MAC_CSR_DATA – MAC CSR Synchronizer Data Register). Table 5.6 LAN9118 MAC CSR Register Map MAC CONTROL AND STATUS REGISTERS INDEX ...
Page 95
... Pass Bad Frames (PASSBAD). When set, all incoming frames that passed address filtering are received, including runt frames and collided frames. 15 Hash Only Filtering mode (HO). When set, the address check Function operates in the Imperfect Address Filtering mode both for physical and multicast addresses 14 Reserved SMSC LAN9118 1 Attribute: 00040000h Size: DESCRIPTION 95 ...
Page 96
... BITS 13 Hash/Perfect Filtering Mode (HPFILT). When reset (0), the LAN9118 will implement a perfect address filter on incoming frames according the address specified in the MAC address register. When set (1), the address check Function does imperfect address filtering of multicast incoming frames according to the hash table specified in the multicast hash table register. ...
Page 97
... Physical Address [47:32]. This field contains the upper 16-bits (47:32) of the Physical Address of the LAN9118 device. The content of this field is undefined until loaded from the EEPROM at power- on. The host can update the contents of this field after the initialization process has completed. ...
Page 98
... Physical Address [31:0]. This field contains the lower 32 bits (31:0) of the Physical Address of the LAN9118 device. The content of this field is undefined until loaded from the EEPROM at power-on. The host can update the contents of this field after the initialization process has completed. ...
Page 99
... HASHL—Multicast Hash Table Low Register Offset: Default Value: This register defines the lower 32-bits of the Multicast Hash Table. Please refer to "HASHH—Multicast Hash Table High Register" BITS 31-0 Lower 32 bits of the 64-bit Hash Table SMSC LAN9118 4 Attribute: 00000000h Size: DESCRIPTION 5 Attribute: ...
Page 100
... MII Busy (MIIBZY): This bit must be polled to determine when the MII register accesss is complete. This bit must read a logical 0 before writing to this register and MII data register. The LAN driver software must set (1) this bit in order for the LAN9118 to read or write any of the MII PHY registers. ...
Page 101
... Enable (FCEN) bit enables the receive portion of the Flow Control block. This register is used in conjunction with the AFC_CFG register in the Slave CSRs to configure flow control. Software flow control is initiated using the AFC_CFG register. Note: The LAN9118 will not transmit pause frames or assert back pressure if the transmitter is disabled. BITS 31-16 Pause Time (FCPT) ...
Page 102
... VLAN2 frame detection.If used, this register must be set to 0x8100. Revision 1.5 (07-11-08) High Performance Single-Chip 10/100 Non-PCI Ethernet Controller 9 Attribute: 00000000h Size: DESCRIPTION A Attribute: 00000000h Size: DESCRIPTION 102 DATASHEET Datasheet R/W 32 bits R/W 32 bits SMSC LAN9118 ...
Page 103
... Wake-Up Frame enabled (WUEN). When set, Remote Wake-Up mode is enabled and the MAC is capable of detecting wake-up frames as programmed in the wake-up frame filter. 1 Magic Packet Enable (MPEN). When set, Magic Packet Wake-up mode is enabled. 0 Reserved SMSC LAN9118 B Attribute: 00000000h Size: DESCRIPTION C Attribute: ...
Page 104
... PHY Register Indexes are shown in Note: The NASR (Not Affected by Software Reset) designation is only applicable when bit 15 of the PHY Basic Control Register (Reset) is set. Table 5.8 LAN9118 PHY Control and Status Register PHY CONTROL AND STATUS REGISTERS INDEX REGISTER NAME ...
Page 105
... Collision Test enable COL test disable COL test 6-0 Reserved Note 5.1 This default value of this bit is determined by Pin 74 "SPEED_SEL". Please refer to the pin description section for more details SMSC LAN9118 0 Size: 105 DATASHEET 16-bits TYPE DEFAULT RW/SC ...
Page 106
... Jabber Detect jabber condition detected jabber condition detected 0 Extended Capabilities supports extended capabilities registers 0 = does not support extended capabilities registers. Revision 1.5 (07-11-08) High Performance Single-Chip 10/100 Non-PCI Ethernet Controller 1 Size: 106 DATASHEET Datasheet 16-bits TYPE DEFAULT RO/ RO/LL 0 RO/ SMSC LAN9118 ...
Page 107
... PHY Identifier 2 Index (In Decimal): BITS DESCRIPTION 15-10 PHY ID Number b. Assigned to the 19th through 24th bits of the OUI Model Number. Six-bit manufacturer’s model number Revision Number. Four-bit manufacturer’s revision number. SMSC LAN9118 2 Size: 3 Size: 107 DATASHEET 16-bits TYPE DEFAULT RO ...
Page 108
... Revision 1.5 (07-11-08) High Performance Single-Chip 10/100 Non-PCI Ethernet Controller 4 Size: 5.2) 108 DATASHEET Datasheet 16-bits TYPE DEFAULT RO 00 R/W 0 R R/W See Note 5.3 R/W 1 R/W See Note 5.3 R/W See Note 5.3 R/W 00001 SMSC LAN9118 ...
Page 109
... Full Duplex with full duplex full duplex ability 7 100Base-TX able ability 6 10Base-T Full Duplex 10Mbps with full duplex 10Mbps with full duplex ability 5 10Base- 10Mbps able 10Mbps ability 4:0 Selector Field. [00001] = IEEE 802.3 SMSC LAN9118 5 Size: 109 DATASHEET 16-bits TYPE DEFAULT ...
Page 110
... Reset to “1” by hardware reset, unaffected by SW reset. 0 Reserved. Write as “0”. Ignore on read. Revision 1.5 (07-11-08) High Performance Single-Chip 10/100 Non-PCI Ethernet Controller 6 Size: 17 Size: 110 DATASHEET Datasheet 16-bits TYPE DEFAULT RO 0 RO/ RO/ 16-bits TYPE DEFAULT SMSC LAN9118 ...
Page 111
... Half Duplex is advertised. Auto- negotiation enabled. CRS is active during Transmit & Receive. 101 Repeater mode. Auto-negotiation enabled. 100Base-TX Half Duplex is advertised. CRS is active during Receive. 110 Reserved - Do not set the LAN9118 in this mode. 111 All capable. Auto-negotiation enabled. SMSC LAN9118 18 Size: DESCRIPTION Table 5.9 for more details ...
Page 112
... INT1. 1= Auto-Negotiation Page Received, 0= not source of interrupt 0 Reserved. Revision 1.5 (07-11-08) High Performance Single-Chip 10/100 Non-PCI Ethernet Controller 27 Size: DESCRIPTION 29 Size: 112 DATASHEET Datasheet 16-bits MODE DEFAULT RW 0 RW, 0 NASR 1011b 16-bits TYPE DEFAULT RO/LH 0 RO/LH 0 RO/LH 0 RO/LH 0 RO/LH 0 RO/LH 0 RO/LH 0 RO/LH 0 RO/LH 0 SMSC LAN9118 ...
Page 113
... Speed Indication. HCDSPEED value: [001]=10Mbps half-duplex [101]=10Mbps full-duplex [010]=100Base-TX half-duplex [110]=100Base-TX full-duplex 1-0 Reserved. Write as 0; ignore on Read Note 5.4 See Table 2.2, “Default Ethernet Settings,” on page SMSC LAN9118 30 Size: 31 Size: 15, for default settings. 113 DATASHEET 16-bits TYPE ...
Page 114
... In order to prevent the host from reading stale data after a write operation, minimum wait periods must be enforced. These periods are specified in processor is required to wait the specified period of time after any write to the LAN9118 before reading the resource specified in the table. These wait periods are for read operations that immediately follow any write cycle ...
Page 115
... FIFO_INT RX_CFG TX_CFG HW_CFG RX_DP_CTRL RX_FIFO_INF TX_FIFO_INF PMT_CTRL GPIO_CFG GPT_CFG GPT_CNT WORD_SWAP FREE_RUN RX_DROP MAC_CSR_CMD MAC_CSR_DATA AFC_CFG E2P_CMD E2P_DATA SMSC LAN9118 Table 6.1 Read After Write Timing Rules MINIMUM WAIT TIME FOR READ FOLLOWING ANY WRITE CYCLE (IN NS) 0 135 135 315 45 ...
Page 116
... There are also restrictions on specific back-to-back read operations. These restrictions concern reading specific registers after reading resources that have side effects. In many cases there is a delay between reading the LAN9118, and the subsequent indication of the expected change in the control register values. ...
Page 117
... Note: Some registers have restrictions on the timing of back-to-back, write-read and read-read cycles. A[7:1] nCS, nRD Data Bus Figure 6.1 LAN9118 PIO Read Cycle Timing Note: The “Data Bus” width is 32 bits with optional support for 16-bit bus widths SYMBOL DESCRIPTION t ...
Page 118
... A[7:5] A[4:1] nCS, nRD Data Bus Figure 6.2 LAN9118 PIO Burst Read Cycle Timing Note: The “Data Bus” width is 32 bits with optional support for 16-bit bus widths SYMBOL DESCRIPTION t nCS, nRD Deassertion Time ...
Page 119
... RX Data FIFO Direct PIO Reads In this mode the upper address inputs are not decoded, and any read of the LAN9118 will read the RX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a read access. This is normally accomplished by connecting the FIFO_SEL signal to high-order address line. This mode is useful when the host processor must increment its address when accessing the LAN9118 ...
Page 120
... RX Data FIFO Direct PIO Burst Reads In this mode the upper address inputs are not decoded, and any burst read of the LAN9118 will read the RX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a read access. This is normally accomplished by connecting the FIFO_SEL signal to a high-order address line. This mode is useful when the host processor must increment its address when accessing the LAN9118 ...
Page 121
... Datasheet 6.6 PIO Writes PIO writes are used for all LAN9118 write cycles. PIO writes can be performed using Chip Select (nCS) or Write Enable (nWR). Either or both of these control signals must go high between cycles for the period specified. PIO Writes are valid for 16- and 32-bit access. Timing for 16-bit and 32-bit PIO write cycles are identical with the exception that D[31:16] are ignored during a 16-bit write ...
Page 122
... TX Data FIFO Direct PIO Writes In this mode the upper address inputs are not decoded, and any write to the LAN9118 will write the TX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a write access. This is normally accomplished by connecting the FIFO_SEL signal to a high-order address line. This mode is useful when the host processor must increment its address when accessing the LAN9118 ...
Page 123
... PARAMETER DESCRIPTION T6.1 Reset Pulse Width T6.2 Configuration input setup to nRST rising T6.3 Configuration input hold after nRST rising T6.4 Output Drive after nRST rising SMSC LAN9118 T6.1 T6.2 T6.3 T6.4 Table 6.9 Reset Timing MIN TYP MAX 200 200 10 16 ...
Page 124
... EEPROM Timing The following specifies the EEPROM timing requirements for the LAN9118 SYMBOL DESCRIPTION t EECLK Cycle time CKCYC t EECLK High time CKH t EECLK Low time CKL t EECS high before rising edge of EECLK CSHCKH t EECLK falling edge to EECS low CKLCSL t EEDIO valid before rising edge of EECLK ...
Page 125
... Section 7.2, "Operating applicable section of this specification is not implied. 7.2 Operating Conditions** Supply Voltage (VDD_A, VDD_REF, VREG, VDD_IO +3.3V +/- 10% Ambient Operating Temperature in Still Air (T **Proper operation of the LAN9118 is guaranteed only within the ranges specified in this section. SMSC LAN9118 (Note 7. .0V to +3.3V+10% (Note 7. +6V (Note 7 ...
Page 126
... Each LED indicator in use adds approximately the Digital power supply. Note 7 Normal Operation WOL (Wake On LAN mode), D2= Low Power Energy Detect. Revision 1.5 (07-11-08) High Performance Single-Chip 10/100 Non-PCI Ethernet Controller TOTAL POWER - TYPICAL (MW) 126 DATASHEET Datasheet 244 225 120 120 35 11 422 367 262 262 35 11 SMSC LAN9118 ...
Page 127
... SMSC Ethernet controller. The values below should be used as comparision measurements only for power provisioning. Please refer to application note “AN 12-5 Designing with the LAN9118 - Getting Started”, that can be found on SMSC’s web site www.smsc.com, which details the magnetics and other components used. ...
Page 128
... VDD - 0.4 0.4 -0.3 0.8 2.0 5.5 0.4 VDD - 0.4 0.4 0.4 VDD - 0.4 -0.3 0.5 1.4 3.6 128 DATASHEET Datasheet UNITS NOTES Schmitt Trigger V Schmitt Trigger 12mA -12mA 12mA 8mA -8mA 8mA 8mA -8mA SMSC LAN9118 ...
Page 129
... Note 7.9 Measured differentially. Table 7.5 10BASE-T Tranceiver Characteristics PARAMETER Transmitter Peak Differential Output Voltage Receiver Differential Squelch Threshold Note 7.10 Measured at the line side of the transformer, line replaced by 100Ω (+/- 1%) resistor. SMSC LAN9118 SYMBOL MIN TYP MAX V 950 - 1050 PPH ...
Page 130
... Clock Circuit The LAN9118 can accept either a 25MHz crystal (preferred MHz clock oscillator (±50 PPM) input. The LAN9118 shares the 25MHz clock oscillator input (CLKIN) with the crystal input XTAL1 (pin 6). If the single-ended clock oscillator method is implemented, XTAL2 should be left unconnected and CLKIN should be driven with a nominal 0-3 ...
Page 131
... Package body dimensions D1 and E1 do not include the mold protrusion. Maximum mold protrusion is 0.25 mm. 4. Dimension for foot length L measured at the gauge plane 0.25 mm above the seating plane. 5. Details of pin 1 identifier are optional but must be located within the zone indicated. SMSC LAN9118 MAX REMARKS 1.60 Overall Package Height 0 ...
Page 132
... Section 7.2, other external devices.” These specifications are not needed by the customer since the regulators are not to be used for external applications. 132 DATASHEET Datasheet CORRECTION WUCSR—Wake- Register, a broadcast wake- Register.” SMSC LAN9118 ...