LAN9118-MD SMSC, LAN9118-MD Datasheet - Page 74
LAN9118-MD
Manufacturer Part Number
LAN9118-MD
Description
Ethernet ICs HiPerfrm Sngl-Chip 10/100 Ethrnt
Manufacturer
SMSC
Type
Single Chip MAC and PHYr
Datasheet
1.LAN9118-MT.pdf
(132 pages)
Specifications of LAN9118-MD
Ethernet Connection Type
10 Base-T, 100 Base-TX
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Product
Ethernet Controllers
Number Of Transceivers
1
Standard Supported
802.3
Data Rate
10 MB, 100 MB
Supply Voltage (max)
3.3 V
Supply Voltage (min)
0 V
Maximum Operating Temperature
+ 70 C
Package / Case
TQFP-100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Revision 1.5 (07-11-08)
5.3.5
5.3.6
31-24
23-16
BITS
BITS
31:0
15-8
7-0
DESCRIPTION
Byte Test
DESCRIPTION
TX Data Available Level. The value in this field sets the level, in number
of 64 Byte blocks, at which the TX FIFO Available interrupt (TFDA) will be
generated. When the TX data FIFO free space is greater than this value a
TX FIFO Available interrupt (TDFA) will be generated.
TX Status Level. The value in this field sets the level, in number of
DWORDs, at which the TX Status FIFO Level interrupt (TSFL) will be
generated. When the TX Status FIFO used space is greater than this value
an TX Status FIFO Level interrupt (TSFL) will be generated.
Reserved
RX Status Level. The value in this field sets the level, in number of
DWORDs, at which the RX Status FIFO Level interrupt (RSFL) will be
generated. When the RX Status FIFO used space is greater than this value
an RX Status FIFO Level interrupt (RSFL) will be generated.
BYTE_TEST—Byte Order Test Register
This register can be used to determine the byte ordering of the current configuration
FIFO_INT—FIFO Level Interrupts
This register configures the limits where the FIFO Controllers will generate system interrupts.
Offset:
Offset:
64h
68h
DATASHEET
74
High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Size:
Size:
32 bits
32 bits
TYPE
TYPE
R/W
R/W
R/W
RO
RO
SMSC LAN9118
87654321h
DEFAULT
DEFAULT
48h
00h
00h
Datasheet
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