LAN9117-MD SMSC, LAN9117-MD Datasheet - Page 122
LAN9117-MD
Manufacturer Part Number
LAN9117-MD
Description
Ethernet ICs HiPerfrm Sngl-Chip 10/100 Ethrnt
Manufacturer
SMSC
Type
Single Chip MAC and PHYr
Datasheet
1.LAN9117-MT.pdf
(136 pages)
Specifications of LAN9117-MD
Ethernet Connection Type
10 Base-T, 100 Base-TX
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Product
Ethernet Controllers
Number Of Transceivers
1
Standard Supported
802.3, 802.3u
Data Rate
10 MB, 100 MB
Supply Voltage (max)
3.3 V
Supply Voltage (min)
0 V
Maximum Operating Temperature
+ 70 C
Package / Case
TQFP-100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LAN9117-MD
Manufacturer:
SMSC
Quantity:
1 831
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In this mode, performance is improved by allowing up to 16, WORD read cycles back-to-back. PIO Burst Reads can
be performed using Chip Select (nCS) or Read Enable (nRD). Either or both of these control signals must go high
between bursts for the period specified.
Revision 1.5 (07-11-08)
6.3
SYMBOL
nCS, nRD
t
t
t
t
t
t
t
t
csdv
acyc
t
asu
adv
don
doff
doh
csh
A[7:5]
A[4:1]
Data Bus
ah
Note: The “Data Bus” width is 16 bits
Note: A PIO Burst Read cycle begins when both nCS and nRD are asserted. The cycle ends when
PIO Burst Reads
DESCRIPTION
nCS, nRD Deassertion Time
nCS, nRD Valid to Data Valid
Address Cycle Time
Address Setup to nCS, nRD valid
Address Stable to Data Valid
Address Hold Time
Data Buffer Turn On Time
Data Buffer Turn Off Time
Data Output Hold Time
either or both nCS and nRD are deasserted. They may be asserted and deasserted in any
order.
Figure 6.2 LAN9117 PIO Burst Read Cycle Timing
Table 6.4 PIO Burst Read Timing
DATASHEET
122
High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
MIN
13
45
0
0
0
0
TYP
MAX
30
40
7
SMSC LAN9117
Datasheet
UNITS
ns
ns
ns
ns
ns
ns
ns
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