LAN9117-MD SMSC, LAN9117-MD Datasheet - Page 72

• Manufacturer Part Number: LAN9117-MD
• Description: Ethernet ICs HiPerfrm Sngl-Chip 10/100 Ethrnt
• Manufacturer: SMSC
• Type: Single Chip MAC and PHYr

Specifications of LAN9117-MD

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: 802.3, 802.3u
• Data Rate: 10 MB, 100 MB
• Supply Voltage (max): 3.3 V
• Supply Voltage (min): 0 V
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Revision 1.5 (07-11-08)
5.3
BASE ADDRESS
+ OFFSET
5Ch
6Ch
7Ch
8Ch
9Ch
50h
54h
58h
60h
64h
68h
70h
74h
78h
80h
84h
88h
90h
94h
98h
A0h
A4h
A8h
The TX data FIFO is write only. It is aliased in 8 DWORD locations (accessed from the bus interface
as 8 pairs of atomic 16-bit accesses). The host write to any of the locations since they all access the
same TX data FIFO location and perform the same function.
Table 5.1, "LAN9117 Direct Address Register
the host bus.
System Control and Status Registers
MAC_CSR_DATA
MAC_CSR_CMD
WORD_SWAP
RX_FIFO_INF
TX_FIFO_INF
BYTE_TEST
RX_DP_CTL
RESERVED
RESERVED
FREE_RUN
PMT_CTRL
GPIO_CFG
RX_DROP
GPT_CFG
GPT_CNT
IRQ_CFG
FIFO_INT
SYMBOL
HW_CFG
INT_STS
RX_CFG
TX_CFG
ID_REV
INT_EN
Table 5.1 LAN9117 Direct Address Register Map
CONTROL AND STATUS REGISTERS
DATASHEET
Chip ID and Revision.
Main Interrupt Configuration
Interrupt Status
Interrupt Enable Register
Reserved for future use
Read-only byte order testing register
FIFO Level Interrupts
Receive Configuration
Transmit Configuration
Hardware Configuration
RX Datapath Control
Receive FIFO Information
Transmit FIFO Information
Power Management Control
General Purpose IO Configuration
General Purpose Timer Configuration
General Purpose Timer Count
Reserved for future use
WORD SWAP Register
Free Run Counter
RX Dropped Frames Counter
MAC CSR Synchronizer Command (MAC
CSR’s are indexed through this register)
MAC CSR Synchronizer Data
72
High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Map", lists the registers that are directly addressable by
REGISTER NAME
See “ID_REV—
Revision” on
Chip ID and
0000FFFFh
0000FFFFh
00000000h
00000000h
00000000h
87654321h
48000000h
00000000h
00000000h
00050000h
00000000h
00000000h
00001200h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
DEFAULT
SMSC LAN9117
page 73.
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Datasheet