SAA7103HB NXP Semiconductors, SAA7103HB Datasheet - Page 47

• Manufacturer Part Number: SAA7103HB
• Description: Video ICs PC GRAPHICS 45MHZ
• Manufacturer: NXP Semiconductors
• Type: Digital Video Encoderr

Specifications of SAA7103HB

• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current: 140 mA
• Maximum Operating Temperature: + 70 C
• Package / Case: QFP-44
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Resolution: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: SAA7103H/V4,557

Philips Semiconductors
SAA7102_SAA7103_4
Product data sheet
Table 41:
Legend: * = default value after reset.
Table 42:
Legend: * = default value after reset.
Table 43:
Legend: * = default value after reset.
Subaddress Bit
27h
26h
Bit
7 and 6 -
5 to 0
Bit
7
6
5 to 0
Symbol Access Value Description
BS[5:0]
Symbol Access Value Description
SRES
-
BE[5:0]
Wide screen signal registers, subaddresses 26h and 27h, bit description
Real-time control and burst start register, subaddress 28h, bit description
Sync reset enable and burst end register, subaddress 29h, bit description
7
6
5 to 3 WSS[13:11] R/W
2 to 0 WSS[10:8]
7 to 4 WSS[7:4]
3 to 0 WSS[3:0]
R/W
R/W
R/W
R/W
R/W
Symbol
WSSON
-
Rev. 04 — 18 January 2006
0
21h*
19h*
0*
1
0
1Dh*
1Dh*
Access Value Description
R/W
R/W
R/W
R/W
R/W
must be programmed with logic 0 to ensure compatibility to
future enhancements
starting point of burst in clock cycles
PAL: BS = 33; strapping pin FSVGC tied to HIGH
NTSC: BS = 25; strapping pin FSVGC tied to LOW
pin TTX_SRES accepts a teletext bit stream (TTX)
pin TTX_SRES accepts a sync reset input (SRES); a HIGH
impulse resets synchronization of the encoder (first field, first
line)
must be programmed with logic 0 to ensure compatibility to
future enhancements
ending point of burst in clock cycles
PAL: BE = 29; strapping pin FSVGC tied to HIGH
NTSC: BE = 29; strapping pin FSVGC tied to LOW
0*
1
0
-
-
-
-
SAA7102; SAA7103
wide screen signalling output is disabled
wide screen signalling output is enabled
must be programmed with logic 0 to ensure
compatibility to future enhancements
wide screen signalling bits, reserved
wide screen signalling bits, subtitles
wide screen signalling bits, enhanced
services
wide screen signalling bits, aspect ratio
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Digital video encoder
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