STV0056A STMicroelectronics, STV0056A Datasheet - Page 17

• Manufacturer Part Number: STV0056A
• Description: Video ICs Analog Sound/Video
• Manufacturer: STMicroelectronics
• Type: Audio DSPr

Specifications of STV0056A

• Maximum Operating Temperature: + 70 C
• Package / Case: PDIP-56
• Minimum Operating Temperature: 0 C
• Mounting Style: Through Hole
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

I
1) WRITING to the chip
S-Start Condition
P-Stop Condition
CHIP ADDR - 7 bits. Programmable 06H or 46H (STV0056A only) with Pin HA.
W-Write/Read bit is the 8th bit of the chip address.
A-ACKNOWLEDGE after receiving 8 bits of data/adress.
REG ADDR
DATA
REG ADDR/A/DATA/A
Example :
2) READING from the chip
When reading, there is an auto-increment feature. This means any read command always starts by reading
Reg 8 and will continue to read the following registers in order after each acknowledge or until there is no
acknowledge or a stop. This function is cyclic that is it will read the same set of registers without
re-addressing the chip. There are two modes of operation as set by writing to bit 7 of register 0. Read 3
registers in a cyclic fashion or all 5 registers in a cyclic fashion. Note only the last 5 of the 11 registers can
be read.
Reg0 bit 7 = L
Reg0 bit 7 = H
CONTROL REGISTERS
Reg 0
Bit (default 00
0
1
2
3
4
5
6
7
Reg 1
Bit (default 00
0
1
2
3
4
5
6
7
2
C PROTOCOL
S
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Select 5 bits audio volume control 00H = MUTE
Select 5 bits audio volume control 01H = -26.75dB
Select 5 bits audio volume control : : : :
Select 5 bits audio volume control 1.25dB steps up to
Select 5 bits audio volume control 1FH = +12dB
Audio mux switch K4 - ANRS I/P select (L = PLL)
Audio mux switch K3 - ANRS select (L = no ANRS, H = ANRS)
L = read 3 registers, H = read 5 registers
Select video gain bits
Select video gain bits
Select video gain bits
Select video gain bits
Select video gain bits
Select video gain bits
Selected video invert (H = inverted, L = non inverted)
Video deemphasis 1 / Video deemphasis 2 (L : V
06
write only
write only
HEX
HEX
W
)
)
Start / chip add / R / A / Reg 8 / A / Reg 9 / A / Reg 0A / A / Reg 8 / A / Reg 9 / A / Reg 0A
/... / P /
Start / chip add / R / A / Reg 8 / A / Reg 9 / A / Reg 0A / A / Reg 7 / A / Reg 6 / A / Reg 8
/ A / Reg 9 / A / Reg 0A / A / Reg 7 / A / Reg 6 / ... / P /
A
Address of register to be written to, 8 bits of which bits 3, 4, 5, 6 & 7 are ’X’ or
don’t care ie only the first 3 bits are used .
8 bits of data being written to the register. All 8 bits must be written to at the same
time.
can be repeated, the write process can continue untill terminated with a STOP
condition. If the REG ADDR is higher than 07 then IIC PROTOCOL will still be
met (ie an A generated).
00
00H = 0dB
01H = +0.202dB
02H = +0.404dB
n
3FH = + 12.73 dB
A
= + 0.202 dB * n
55
A
:
01
ID
De-em 1)
A
8F
STV0056A
A
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P