IRF840ASPBF Vishay, IRF840ASPBF Datasheet - Page 4

• Manufacturer Part Number: IRF840ASPBF
• Description: MOSFET N-CH 500V 8A D2PAK
• Manufacturer: Vishay
• Type: Power MOSFETr

Specifications of IRF840ASPBF

• Transistor Polarity: N-Channel
• Fet Type: MOSFET N-Channel, Metal Oxide
• Fet Feature: Standard
• Rds On (max) @ Id, Vgs: 850 mOhm @ 4.8A, 10V
• Drain To Source Voltage (vdss): 500V
• Current - Continuous Drain (id) @ 25° C: 8A
• Vgs(th) (max) @ Id: 4V @ 250µA
• Gate Charge (qg) @ Vgs: 38nC @ 10V
• Input Capacitance (ciss) @ Vds: 1018pF @ 25V
• Power - Max: 3.1W
• Mounting Type: Surface Mount
• Package / Case: D²Pak, TO-263 (2 leads + tab)
• Minimum Operating Temperature: - 55 C
• Configuration: Single
• Resistance Drain-source Rds (on): 0.85 Ohm @ 10 V
• Drain-source Breakdown Voltage: 500 V
• Gate-source Breakdown Voltage: +/- 30 V
• Continuous Drain Current: 8 A
• Power Dissipation: 3100 mW
• Maximum Operating Temperature: + 150 C
• Mounting Style: SMD/SMT
• Continuous Drain Current Id: 8A
• Drain Source Voltage Vds: 500V
• On Resistance Rds(on): 850mohm
• Rds(on) Test Voltage Vgs: 10V
• Threshold Voltage Vgs Typ: 4V
• Number Of Elements: 1
• Polarity: N
• Channel Mode: Enhancement
• Drain-source On-res: 0.85Ohm
• Drain-source On-volt: 500V
• Gate-source Voltage (max): ±30V
• Output Power (max): Not RequiredW
• Frequency (max): Not RequiredMHz
• Noise Figure: Not RequireddB
• Power Gain: Not RequireddB
• Drain Efficiency: Not Required%
• Operating Temp Range: -55C to 150C
• Operating Temperature Classification: Military
• Mounting: Surface Mount
• Pin Count: 2 +Tab
• Package Type: D2PAK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: *IRF840ASPBF

IRF840AS, SiHF840AS, IRF840AL, SiHF840AL
Vishay Siliconix
www.vishay.com
4
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
91066_05
91066_06
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
10
10
10
10
10
20
16
12
1
8
4
0
5
4
3
2
0
1
I
D
= 8.0 A
V
DS ,
Q
10
G
Drain-to-Source Voltage (V)
V
, Total Gate Charge (nC)
DS
10
= 100 V
V
V
C
C
C
DS
GS
iss
rss
oss
20
= 250 V
= 0 V, f = 1 MHz
= C
= C
= C
V
DS
gs
gd
ds
= 400 V
+ C
C
C
C
+ C
10
rss
iss
oss
2
gd
gd
For test circuit
see figure 13
, C
This document is subject to change without notice.
30
ds
Shorted
10
40
3
91066_08
91066_07
Fig. 7 - Typical Source-Drain Diode Forward Voltage
10
10
0.1
0.1
10
10
Fig. 8 - Maximum Safe Operating Area
1
1
2
2
0.2
10
Operation in this area limited
T
V
J
V
DS
= 150
SD
by R
, Drain-to-Source Voltage (V)
0.5
, Source-to-Drain Voltage (V)
°
DS(on)
C
10
2
0.8
S11-1050-Rev. D, 30-May-11
www.vishay.com/doc?91000
T
Document Number: 91066
J
1
= 25
10
100
10
ms
µs
10
ms
µs
°
3
C
1.1
T
T
Single Pulse
C
J
V
= 150 °C
= 25 °C
GS
= 0 V
1.4
10
4