SI3201-FSR Silicon Laboratories Inc, SI3201-FSR Datasheet - Page 106

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SI3201-FSR

Manufacturer Part Number
SI3201-FSR
Description
SLIC 1-CH 60dB 41mA 3.3V/5V 16-Pin SOIC EP T/R
Manufacturer
Silicon Laboratories Inc
Datasheet

Specifications of SI3201-FSR

Package
16SOIC EP
Number Of Channels Per Chip
1
Longitudinal Balanced
60 dB
Loop Current
41 mA
Minimum Operating Supply Voltage
3.13 V
Typical Operating Supply Voltage
3.3|5 V
Typical Supply Current
88 mA

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Quantity
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Part Number:
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SILICON LABS/芯科
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14
Receive Path Digital to Analog Converter Gain/Attenuation.
This register sets gain/attenuation for the receive path. The digitized signal is effectively mul-
tiplied by DACG to achieve gain/attenuation. A value of 0x00 corresponds to –  dB gain
(mute). A value of 0x400 corresponds to unity gain. A value of 0x7FF corresponds to a gain
of 6 dB.
Transmit Path Analog to Digital Converter Gain/Attenuation.
This register sets gain/attenuation for the transmit path. The digitized signal is effectively
multiplied by ADCG to achieve gain/attenuation. A value of 0x00 corresponds to –  dB gain
(mute). A value of 0x400 corresponds to unity gain. A value of 0x7FF corresponds to a gain
of 6 dB.
Table 39. Digital Programmable Gain/Attenuation Indirect Registers Description
Description
Rev. 1.0
Reference
Page
43
43

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