SI3201-KS Silicon Laboratories Inc, SI3201-KS Datasheet

IC LINEFEED INTRFC SI321X 16SOIC

SI3201-KS

Manufacturer Part Number
SI3201-KS
Description
IC LINEFEED INTRFC SI321X 16SOIC
Manufacturer
Silicon Laboratories Inc
Series
ProSLIC®r
Datasheet

Specifications of SI3201-KS

Package / Case
16-SOIC (3.9mm Width) Exposed Pad, 16-eSOIC, 16-HSOIC
Function
CODEC
Interface
PCM, Serial, SPI
Number Of Circuits
1
Voltage - Supply
3.13 V ~ 5.25 V
Current - Supply
88mA
Power (watts)
800mW
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Includes
BORSCHT Functions, Ring Trip Detection
Product
SLIC
Supply Voltage (min)
3.13 V
Supply Current
88 mA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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P
W I T H
Features
Applications
Description
The ProSLIC
telephone interface ideal for customer premise equipment (CPE) applications. The
ProSLIC integrates a subscriber line interface circuit (SLIC), codec, and battery
generation functionality into a single CMOS integrated circuit. The integrated battery
supply continuously adapts its output voltage to minimize power and enables the entire
solution to be powered from a single 3.3 V (Si3210M/Si3211M only) or 5 V supply. The
ProSLIC controls the phone line through Silicon Labs’ Si3201 Linefeed Interface Chip.
Si3210 features include software-configurable 5 REN internal ringing up to 90 V
DTMF generation and decoding, and a comprehensive set of telephony signaling
capabilities for operation with only one hardware solution. The ProSLIC is packaged in
a 38-pin QFN and TSSOP, and the Si3201 is packaged in a thermally-enhanced 16-pin
SOIC.
Functional Block Diagram
Rev. 1.45 1/09
RO
Performs all BORSCHT functions
Software-programmable internal balanced
ringing up to 90 V
(5 REN up to 4 kft, 3 REN up to 8 kft)
Integrated battery supply with dynamic
voltage output (Si3210)





Software-programmable linefeed
parameters




Voice-over-broadband systems:
DSL, codec, wireless
PBX/IP-PBX/key telephone systems
minimizes power in all operating modes
Entire solution can be powered from a single
3.3 or 5 V supply
transformer versions supported
waveform
filtering
On-chip dc-dc converter continuously
3.3 to 35 V dc input range
Dynamic 0 to –94.5 V output
Low-cost inductor and high-efficiency
Ringing frequency, amplitude, cadence, and
2-wire ac impedance and hybrid
Constant current feed (20 to 41 mA)
Loop closure and ring trip thresholds and
SLIC
R
®
FSYNC
SCLK
PCLK
SDO
DRX
DTX
SDI
CS
is a low-voltage CMOS device that provides a complete analog
INGING
INT
PK
Interface
Interface
Control
PCM
®
PLL
RESET
P
ROGRAMMABLE
/ B
Attenuation/
Attenuation/
Generators
Decode
DTMF
Gain/
Gain/
Filter
Tone
Filter
Si3210/11
A TT E R Y
D/A
A/D
Copyright © 2009 by Silicon Laboratories
DC-DC Converter Controller
Hybrid
Prog.
(Si3210 only)
Software-programmable signal
generation and audio processing






Extensive test and diagnostic features



SPI and PCM bus digital interfaces
Extensive programmable interrupts
100% software-configurable global
solution
Ideal for customer premise equipment
applications
RoHS-compliant packages available
Terminal adapters:
ISDN, Ethernet, USB
generation
audio
DTMF generation and decoding
12 kHz/16 kHz pulse metering generation
Phase-continuous FSK (caller ID)
Dual audio tone generators
Smooth and abrupt polarity reversal
µ-Law/A-Law and 16-bit linear PCM
Multiple voice loopback test modes
Real-time dc linefeed measurement
GR-909 line test capabilities
Status
Control
Z
Line
Feed
Line
S
V
OLTA GE
Components
Linefeed
Interface
Discrete
CMOS SLIC/C
TIP
RING
S i 3 2 1 0 / S i 3 2 11
G
PK
ENERATION
,
U.S. Patent #6,567,521
U.S. Patent #6,812,744
Other patents pending
SDCH/DIO1
SDCL/DIO2
SRINGDC
SRINGE
STIPDC
FSYNC
RESET
SVBAT
TSSOP Pin Assignments
QGND
CAPM
STIPE
CAPP
PCLK
V
IREF
DRX
DTX
Ordering Information
DDA1
INT
CS
See page 129.
ODEC
Si3210/11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
SCLK
SDI
SDO
SDITHRU
DCDRV/DCSW
TEST
GNDD
ITIPN
ITIPP
IRINGP
IRINGN
IGMP
GNDA
IGMN
SRINGAC
STIPAC
DCFF/DOUT
VDDD
V
DDA2
Si3210

Related parts for SI3201-KS

SI3201-KS Summary of contents

Page 1

... Si3210 features include software-configurable 5 REN internal ringing DTMF generation and decoding, and a comprehensive set of telephony signaling capabilities for operation with only one hardware solution. The ProSLIC is packaged in a 38-pin QFN and TSSOP, and the Si3201 is packaged in a thermally-enhanced 16-pin SOIC. Functional Block Diagram ...

Page 2

Si3210/Si3211 2 Rev. 1.45 ...

Page 3

... Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 4.3. Digital Programmable Gain/Attenuation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 4.4. SLIC Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 4.5. FSK Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124 5. Pin Descriptions: Si3210/ 125 6. Pin Descriptions: Si3201 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 7. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 8. Package Outline: 38-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 9. Package Outline: 38-Pin TSSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 10. Package Outline: 16-Pin ESOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Document Change List ...

Page 4

... Operation above 125 °C junction temperature may degrade device reliability. 3. Thermal resistance assumes a multi-layer PCB with the exposed pad soldered to a topside PCB pad Symbol Si3210/ DDD DDA1 DDA2 IND STG  JA  Si3201 BAT V INHV STG 3  Rev. 1.45 Value Unit –0.5 to 6.0 V ±10 mA –0 ...

Page 5

... Ambient Temperature Si3210/11 Supply Voltage Si3201 Supply Voltage Si3201 Battery Voltage *Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise stated. Product specifications are only guaranteed for the typical application circuit (including component tolerances). ...

Page 6

... Hz to 3.4 kHz,   Q1,Q2 150, 1% mismatch   240 5 Q1,Q2   300 to 800 5 Q1,Q2 Using Si3201 200 Hz to 3.4 kHz 200 Hz to 3.4 kHz at TIP or RING Register selectable ETBO/ETBA Active off-hook 200 Hz to 3.4 kHz Register selectable ...

Page 7

Figure 1. Transmit and Receive Path SNDR Fundamental 5 Output Power (dBm0 2 Fundamental Input Power (dBm0) Figure 2. Overload Compression Performance Rev. 1.45 Si3210/Si3211 Acceptable Region 4 ...

Page 8

Si3210/Si3211 Figure 3. Transmit Path Frequency Response 8 Typical Response Typical Response Rev. 1.45 ...

Page 9

Figure 4. Receive Path Frequency Response Rev. 1.45 Si3210/Si3211 9 ...

Page 10

Si3210/Si3211 Figure 5. Transmit Group Delay Distortion Figure 6. Receive Group Delay Distortion 10 Rev. 1.45 ...

Page 11

Table 4. Linefeed Characteristics ( 3. 70°C for K-Grade, –40 to 85°C for B-Grade) DDA DDD A Parameter Symbol Loop Resistance Range* R LOOP DC Loop Current Accuracy DC Open ...

Page 12

Si3210/Si3211 Table 5. Monitor ADC Characteristics ( 3. °C for K-Grade, – °C for B-Grade) DDA DDD A Parameter Symbol Differential Nonlinearity DNLE (6-bit resolution) Integral Nonlinearity ...

Page 13

... Sleep (RESET = 0) Open (DCOF = 1) Active on-hook ETBO = Active OHT ETBO = 4 mA BAT Active off-hook ETBA = 4 mA LIM Ground Start Ringing PK_RING Sinewave ringing: REN = 1 When using Si3201 x V BAT BAT Rev. 1.45 Si3210/Si3211 1 2 Max Typ Typ 0.1 0.13 0 ...

Page 14

Si3210/Si3211 Table 9. Switching Characteristics (General Inputs 3. °C for K-Grade, – °C for B-Grade, C DDA DDA A Parameter Rise Time, RESET RESET Pulse Width ...

Page 15

Table 10. Switching Characteristics (SPI 3. °C for K-Grade, – °C for B-Grade, C DDA DDA A Parameter Cycle Time SCLK Rise Time, SCLK Fall Time, ...

Page 16

Si3210/Si3211 Table 11. Switching Characteristics—PCM Highway Serial Interface V = 3. °C for K-Grade, – °C for B-Grade Parameter PCLK Frequency PCLK Duty Cycle Tolerance PCLK-to-FSYNC Jitter ...

Page 17

... Only one component per system needed. 3. All circuit ground should have a single-point connection to the ground plane. 4. Si3201 bottom-side exposed pad should be electrically and thermally connected to bulk ground plane. 5. Pin numbers for TSSOP shown. Figure 9. Si3210/Si3210M Application Circuit Using Si3201 R1 200k 15 STIPDC 20 STIPAC C24 0.1  ...

Page 18

... Si3210/Si3211 Table 12. Si3210/Si3210M + Si3201 External Component Values Component(s) 10 µ Ceramic Low Leakage C1,C2 Electrolytic, ±20% C3,C4 220 nF, 100 V, X7R, ±20% C5,C6 22 nF, 100 V, X7R, ±20% C15,C16,C17,C24 0.1 µ Y5V, ±20% C18,C19 4.7 µF, ceramic X7R, ±20% C26 0.1 µF, 100 V, X7R, ±20% C30,C31 10 µ ...

Page 19

SDCH 1 R19 Note 1 1 R20 SDCL C10 R16 0.1 µF 200 DCFF 2N2222 DCDRV Notes: 1. Values and configurations for these components can be derived from “AN45: Design Guide for the Si3210 DC-DC Converter” or Table 21. 2. ...

Page 20

Si3210/Si3211 Table 13. Si3210 BJT/Inductor DC-DC Converter Component Values Component( µF, 100 V, Electrolytic, ±20% C10 0.1 µ X7R, ±20% C14* 0.1 µF, X7R, ±20% C25* 10 µF, Electrolytic, ±20% 200 , 1/10 W, ±5% R16 ...

Page 21

SDCH SDCL DCFF DCDRV NC Notes: 1. Values and configurations for these components can be derived from AN45 or Table 20. 2. Voltage rating for C14 and C25 must be greater than VDC. Figure 11. Si3210M MOSFET/Transformer DC-DC Converter Circuit ...

Page 22

... Only one component per system needed. 2. All circuit grounds should have a single- point connection to the ground plane. 3. Si3201 bottom-side exposed pad should be electrically and thermally connected to bulk ground plane. 4. Pin numbers for TSSOP shown. Figure 12. Si3211 Typical Application Circuit Using Si3201 22 C31 R1 200k 15 STIPDC ...

Page 23

... Table 15. Si3211 + Si3201 External Component Values Component(s) C1,C2 10 µ Ceramic Low-Leakage Electrolytic, ±20% C3,C4 220 nF, 100 V, X7R, ±20% C5,C6 22 nF, 100 V, X7R, ±20% C9 0.1 µF, 100 V, X7R, ±20% C15,C16,C17,C24 0.1 µ Y5V, ±20% C18,C19 4.7 µF Ceramic X7R, ±20% C30,C31 10 µ Electrolytic, ±20 µ ...

Page 24

Si3210/Si3211 Q1 5401 R10 10 TIP Q6 5551 C8 C5 220nF 22nF Protection Circuit R6 C6 80.6 22nF RING C26 0.1 µF Notes: 1. Values and configurations for these compo- nents can be derived from Table 19 or from “AN45: ...

Page 25

Table 16. Si3210/Si3210M External Component Values—Discrete Solution Component(s) Value 10 µ Ceramic Low-Leakage C1,C2 Electrolytic, 20% 220 nF, 100 V, X7R, 20% C3,C4 22 nF, 100 V, X7R, 20% C5,C6 220 nF X7R, ...

Page 26

Si3210/Si3211 Q1 5401 R10 10 TIP Q6 5551 C8 C5 220nF 22nF Protection Circuit R6 C6 80.6 22nF RING C26 0.1 µF Notes: 1. Only one component per system needed. 2. All circuit grounds should have a single-point connection to ...

Page 27

Table 17. Si3211 External Component Values—Discrete Solution Component(s) 10 µ Ceramic Low Leakage C1,C2 Electrolytic, 20% 220 nF, 100 V, X7R, 20% C3,C4 22 nF, 100 V, X7R, 20% C5,C6 220 nF X7R, ...

Page 28

Si3210/Si3211 QRP Q5 5551 R7 R12 RRE RRBN 80.6 5.1k Figure 15. Si321x Optional Equivalent Q5, Q6 Table 18. Si321x Optional Bias Component Values Component 100 nF, 100 V, X7R, 20% C7,C8 3.0 k, 1/10 W, 5% R23,R24 The subcircuit ...

Page 29

Table 20. Component Value Selection Examples for Si3210M MOSFET/Transformer DC-DC Converter VDC Maximum Ringing Load/Loop Resistance 3 REN/117  3 REN/117  5 REN/117  REN/117  Note: There are other ...

Page 30

... DTMF decoding and pulse metering signal generation are also integrated. The Si3201 linefeed interface IC performs all high-voltage functions option, the Si3201 can also be replaced with low- cost discrete components as shown in the typical application circuits in Figures 12, 13, and 14. ...

Page 31

... Linefeed Architecture The ProSLIC is a low-voltage CMOS device that uses either an Si3201 linefeed interface IC or low-cost external components to control the high voltages required for subscriber line interfaces. Figure simplified illustration of the linefeed control loop circuit for TIP or RING and the external components used. ...

Page 32

... Ringing 101 Reverse Active 110 Reverse On-Hook Transmission 111 Ring Open Note: The linefeed register (LF) is located in direct Register 64. 32 Monitor A/D A/D DSP D/A SLIC DAC  Control DC Sense Si3201 Control Loop Description TIP and RING tri-stated V > V TIP ...

Page 33

Table 24. Measured Real-Time Linefeed Interface Characteristics Parameter Loop Voltage Sense (V – V TIP RING Loop Current Sense TIP Voltage Sense RING Voltage Sense Battery Voltage Sense BAT Battery Voltage Sense BAT Transistor ...

Page 34

Si3210/Si3211 Table 25. Associated Power Monitoring and Power Fault Registers Parameter Power Monitor Pointer Line Power Monitor Output Power Alarm Threshold, Q1 & Q2 Power Alarm Threshold, Q3 & Q4 Power Alarm Threshold, Q5 & Q6 Thermal LPF Pole, Q1 ...

Page 35

LCS Input ISP_OUT Signal LVS Processor LFS LCVE 2.1.6. Loop Closure Transition Detection A loop closure transition event signals that the terminal equipment has gone from on-hook to off-hook or from off-hook to on-hook; detection occurs while the ProSLIC linefeed ...

Page 36

... Calibration should be performed in the on-hook state. RING or TIP must not be connected to ground during the calibration. When using the Si3201, automatic calibration routines for RING gain mismatch and TIP gain mismatch should not be performed. Instead of running these two calibrations automatically, follow the instructions for manual calibration in “ ...

Page 37

MOSFET/Transformer Circuit Option Using the Si3210M The MOSFET/transformer circuit option (shown in Figure 11 on page 21) offers higher power efficiencies across a larger input voltage range. Depending on the transformer’s primary inductor value and the switching frequency, the ...

Page 38

Si3210/Si3211 The power dissipation on the NPN bipolar transistor driving the RING terminal can become large and may require a higher power rating device. The non-tracking mode of operation is required by specific terminal equipment that, in order to initiate ...

Page 39

DC-DC Converter Enhancements Silicon revisions C and higher enhancements to the dc-dc converter. The first is a multi-threshold error control algorithm that enables the dc-dc converter to adjust more quickly to voltage changes. This option is enabled by setting ...

Page 40

Si3210/Si3211 8 kHz Clock OnE Zero 16-Bit Cross OAT Modulo Logic Expire Counter OIT Expire OATn OATnE OITn OITnE *Tone Generator 1 Only n = "1" or "2" for Tone Generator 1 and 2, respectively Figure 20. Simplified Tone Generator ...

Page 41

The cadence continues until the user clears the O1TAE and O1TIE control bits. The zero crossing detect feature can be implemented by setting the ...

Page 42

Si3210/Si3211 O1E ... ... 0 AT1 OSS1 Tone Gen. 1 Signal Output Figure 21. Tone Generator Timing Diagram 2.3.4. Enhanced FSK Waveform Generation Silicon revisions C and higher support enhanced FSK generation capabilities, which can be enabled by ...

Page 43

Table 30. Registers for Ringing Generation Parameter Ringing Waveform Ringing Voltage Offset Enable Ringing Active Timer Enable Ringing Inactive Timer Enable Ringing Oscillator Enable Ringing Oscillator Active Timer Ringing Oscillator Inactive Timer Linefeed Control (Initiates Ringing State) High Battery Voltage ...

Page 44

Si3210/Si3211 15    RCO 0.99211 2 32509 = = 1 70 0.00789 15    ----- - RNGX = -------------------- - 1.99211 RNGY addition, the user must select the ...

Page 45

N is the ringing REN load (max value = 5), REN I is the offset current flowing in the line driver circuit OS (max value = 2 mA), and V = amplitude of the ac ringing waveform. AC,PK It ...

Page 46

Si3210/Si3211 Table 31. Associated Registers for Ring Trip Detection Parameter Ring Trip Interrupt Pending Ring Trip Interrupt Enable Ring Trip Detect Debounce Interval Ring Trip Threshold Ring Trip Filter Coefficient Ring Trip Detect Status (monitor only) Note: The ProSLIC uses ...

Page 47

Table 33. Associated Pulse Metering Generator Registers Parameter Pulse Metering Frequency Coefficient Pulse Metering Amplitude Coefficient Pulse Metering Attack/Decay Ramp Rate Pulse Metering Active Timer Pulse Metering Inactive Timer Pulse Metering Control Status and control registers Note: The ProSLIC uses ...

Page 48

Si3210/Si3211 2.7. Audio Path Unlike traditional SLICs, the codec function is integrated into the ProSLIC. The 16-bit codec offers programmable gain/attenuation blocks and several loopback modes. The signal path block diagram is shown in Figure 25. 2.7.1. Transmit Path In ...

Page 49

Si3210/Si3211 Rev. 1.45 49 ...

Page 50

Si3210/Si3211 2.7.2. Receive Path In the receive path, the optionally-compressed 8-bit data is first expanded to 16-bit words. The PCMF register bit can bypass the expansion process, in which case two 8-bit words are assembled into one 16- bit word. ...

Page 51

An additional analog loopback (ALM1) takes the digital stream at the output of the A/D converter and feeds it back to the D/A converter. (See ...

Page 52

Si3210/Si3211  Pulse metering active timer expired  Pulse metering inactive timer expired  Indirect register access complete The interface to the interrupt logic consists of six registers. Three interrupt status registers contain one bit for each of the above ...

Page 53

SCLK CS SDI SDO SCLK CS SDI SDO High Impedance Don't Care High Impedance Figure 26. Serial Write 8-Bit Mode Don't Care ...

Page 54

Si3210/Si3211 SDO CPU CS SDI Chip Select Byte SCLK SDI0 SDI1 – SDI2 – – SDI3 – – – ...

Page 55

PCM Interface The ProSLIC contains a flexible programmable interface for the transmission and reception of digital PCM samples. PCM data transfer is controlled via the PCLK and FSYNC inputs as well as PCM Mode Select (direct Register 1), PCM ...

Page 56

Si3210/Si3211 Figure 30. Example, Timeslot 1, Long FSYNC (TXS/RXS = 0) PCLK FSYNC PCLK_CNT 0 1 DRX DTX HI-Z Figure 31. Example, IDL2 Long FSYNC, B2, 10-Bit Mode (TXS/RXS = 10) PCLK FSYNC 0 1 PCLK_CNT DRX MSB DTX HI-Z ...

Page 57

Table 34. µ-Law Encode-Decode Characteristics Segment #Intervals X Interval Size Number 256 128 ...

Page 58

Si3210/Si3211 Table 35. A-Law Encode-Decode Characteristics Segment #intervals X interval size Number 128 ...

Page 59

Control Registers Note: Any register not listed here is reserved and must not be written. Register Name 0 SPI Mode Select 1 PCM Mode Select 2 PCM Transmit Start Count—Low Byte 3 PCM Transmit Start Count—High Byte 4 PCM ...

Page 60

Si3210/Si3211 Table 36. Direct Register Summary (Continued) Register Name 28 Indirect Data Access— Low Byte 29 Indirect Data Access— High Byte 30 Indirect Address 31 Indirect Address Status 32 Oscillator 1 Control 33 Oscillator 2 Control 34 Ringing Oscillator Control ...

Page 61

Table 36. Direct Register Summary (Continued) Register Name 47 Pulse Metering Oscillator Inactive Timer—High Byte 48 Ringing Oscillator Active Timer—Low Byte 49 Ringing Oscillator Active Timer—High Byte 50 Ringing Oscillator Inac- tive Timer—Low Byte 51 Ringing Oscillator Inac- tive Timer—High ...

Page 62

Si3210/Si3211 Table 36. Direct Register Summary (Continued) Register Name 79 Loop Current Sense 80 TIP Voltage Sense 81 RING Voltage Sense 82 Battery Voltage Sense 1 83 Battery Voltage Sense 2 84 Transistor 1 Current Sense 85 Transistor 2 Current ...

Page 63

Table 36. Direct Register Summary (Continued) Register Name 102 Current Limit Calibration Result 103 Monitor ADC Offset Calibration Result 104 Analog DAC/ADC Offset 105 DAC Offset Calibration Result 106 Common Mode Balance Calibration Result 107 DC Peak Current Calibration Result ...

Page 64

Si3210/Si3211 Register 0. SPI Mode Select Bit D7 D6 Name SPIDC SPIM Type R/W R/W Reset settings = 00xx_xxxx Bit Name 7 SPIDC SPI Daisy Chain Mode Enable Disable SPI daisy chain mode Enable SPI daisy ...

Page 65

Register 1. PCM Mode Select Bit D7 D6 Name PNI2 Type Reset settings = 0000_1000 Bit Name 7 PNI2 Part Number Identification Si3210/11 family Si3215/16 family. 6 Reserved Read returns zero. 5 PCME PCM Enable. ...

Page 66

Si3210/Si3211 Register 2. PCM Transmit Start Count—Low Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 TXS[7:0] PCM Transmit Start Count. PCM transmit start count equals the number of PCLKs following FSYNC before data trans- mission ...

Page 67

Register 5. PCM Receive Start Count—High Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:2 Reserved Read returns zero. 1:0 RXS[9:8] PCM Receive Start Count. PCM receive start count equals the number of PCLKs following FSYNC ...

Page 68

Si3210/Si3211 Bit Name 7:5 Reserved Read returns zero. 4 DOUT DOUT Pin Output Data (Si3211 only DOUT pin driven low DOUT pin driven high. Si3210 = Reserved. 3 DIO2 DIO2 Pin Input/Output Direction (Si3211 only). 0 ...

Page 69

Register 8. Audio Path Loopback Control Bit D7 D6 Name Type Reset settings = 0000_0010 Bit Name 7:3 Reserved Read returns zero. 2 ALM2 Analog Loopback Mode 2. (See Figure 25 on page 49 Full analog loopback mode ...

Page 70

Si3210/Si3211 Register 9. Audio Gain Control Bit D7 D6 Name RXHP TXHP Type R/W R/W Reset settings = 0000_0000 Bit Name 7 RXHP Receive Path High Pass Filter Disable HPF enabled in receive path, RHDF HPF ...

Page 71

Register 10. Two-Wire Impedance Synthesis Control Bit D7 D6 Name Type Reset settings = 0000_1000 Bit Name 7:6 Reserved Read returns zero. 5:4 CLC[1:0] Line Capacitance Compensation Off ...

Page 72

Si3210/Si3211 Register 11. Hybrid Control Bit D7 D6 Name Type Reset settings = 0011_0011 Bit Name 7 Reserved Read returns zero. 6:4 HYBP[2:0] Pulse Metering Hybrid Adjustment. 000 = 4.08 dB 001 = 2.5 dB 010 = 1.16 dB 011 ...

Page 73

Register 14. Powerdown Control 1 Bit D7 D6 Name Type Reset settings = 0001_0000 Bit D7 D6 Name Type Reset settings = 0001_0000 Bit Name 7:6 Reserved Read returns zero. 5 PMON Pulse Metering DAC Power-On Control Automatic ...

Page 74

Si3210/Si3211 Register 15. Powerdown Control 2 Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:6 Reserved Read returns zero. 5 ADCM Analog to Digital Converter Manual/Automatic Power Control Automatic power control Manual power ...

Page 75

Register 18. Interrupt Status 1 Bit D7 D6 Name PMIP PMAP Type R/W R/W Reset settings = 0000_0000 Bit Name 7 PMIP Pulse Metering Inactive Timer Interrupt Pending. Writing 1 to this bit clears a pending interrupt ...

Page 76

Si3210/Si3211 Register 19. Interrupt Status 2 Bit D7 D6 Name Q6AP Q5AP Type R/W R/W Reset settings = 0000_0000 Bit Name 7 Q6AP Power Alarm Q6 Interrupt Pending. Writing 1 to this bit clears a pending interrupt ...

Page 77

Register 20. Interrupt Status 3 Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:3 Reserved Read returns zero. 2 CMCP Common Mode Calibration Error Interrupt. This bit is set when off-hook/on-hook status changes during the common mode ...

Page 78

Si3210/Si3211 Register 21. Interrupt Enable 1 Bit D7 D6 Name PMIE PMAE Type R/W R/W Reset settings = 0000_0000 Bit Name 7 PMIE Pulse Metering Inactive Timer Interrupt Enable Interrupt masked Interrupt enabled. 6 PMAE Pulse ...

Page 79

Register 22. Interrupt Enable 2 Bit D7 D6 Name Q6AE Q5AE Type R/W R/W Reset settings = 0000_0000 Bit Name 7 Q6AE Power Alarm Q6 Interrupt Enable Interrupt masked Interrupt enabled. 6 Q5AE Power Alarm Q5 ...

Page 80

Si3210/Si3211 Register 23. Interrupt Enable 3 Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:3 Reserved Read returns zero. 2 CMCE Common Mode Calibration Error Interrupt Enable Interrupt masked Interrupt enabled. 1 INDE ...

Page 81

Register 24. DTMF Decode Status Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:5 Reserved Read returns zero. 4 VAL DTMF Valid Digit Decoded Not currently detecting digit Currently detecting digit. 3:0 DIG[3:0] ...

Page 82

Si3210/Si3211 Register 28. Indirect Data Access—Low Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 IDA[7:0] Indirect Data Access—Low Byte. A write to IDA followed by a write to IAA will place the contents of IDA ...

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Register 30. Indirect Address Bit D7 D6 Name Type Reset settings = xxxx_xxxx Bit Name 7:0 IAA[7:0] Indirect Address Access. A write to IDA followed by a write to IAA will place the contents of IDA into an indirect register ...

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Si3210/Si3211 Register 32. Oscillator 1 Control Bit D7 D6 Name OSS1 REL Type R R/W Reset settings = 0000_0000 Bit Name 7 OSS1 Oscillator 1 Signal Status Output signal inactive Output signal active. 6 REL Oscillator ...

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Register 33. Oscillator 2 Control Bit D7 D6 Name OSS2 Type R Reset settings = 0000_0000 Bit Name 7 OSS2 Oscillator 2 Signal Status Output signal inactive Output signal active. 6 Reserved Read returns zero. 5 ...

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Si3210/Si3211 Register 34. Ringing Oscillator Control Bit D7 D6 Name RSS Type R Reset settings = 0000_0000 Bit Name 7 RSS Ringing Signal Status Ringing oscillator output signal inactive Ringing oscillator output signal active. 6 Reserved ...

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Register 35. Pulse Metering Oscillator Control Bit D7 D6 Name PSTAT Type R Reset settings = 0000_0000 Bit Name 7 PSTAT Pulse Metering Signal Status Output signal inactive Output signal active. 6:5 Reserved Read returns zero. ...

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Si3210/Si3211 Register 37. Oscillator 1 Active Timer—High Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 OAT1[15:8] Oscillator 1 Active Timer. Register 38. Oscillator 1 Inactive Timer—Low Byte Bit D7 D6 Name Type Reset settings = ...

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Register 40. Oscillator 2 Active Timer—Low Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 OAT2[7:0] Oscillator 2 Active Timer. LSB = 125 µs Register 41. Oscillator 2 Active Timer—High Byte Bit D7 D6 Name Type ...

Page 90

Si3210/Si3211 Register 43. Oscillator 2 Inactive Timer—High Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 OIT2[15:8] Oscillator 2 Inactive Timer. Register 44. Pulse Metering Oscillator Active Timer—Low Byte Bit D7 D6 Name Type Reset settings ...

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Register 46. Pulse Metering Oscillator Inactive Timer—Low Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 PIT[7:0] Pulse Metering Inactive Timer. LSB = 125 µs Register 47. Pulse Metering Oscillator Inactive Timer—High Byte Bit D7 D6 ...

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Si3210/Si3211 Register 49. Ringing Oscillator Active Timer—High Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 RAT[15:8] Ringing Active Timer. Register 50. Ringing Oscillator Inactive Timer—Low Byte Bit D7 D6 Name Type Reset settings = 0000_0000 ...

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Register 52. FSK Data Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:1 Reserved Read returns zero. 0 FSKDAT FSK Data. When FSKEN = 1 (direct Register 108, bit 6) and REL = 1 (direct Register 32, ...

Page 94

Si3210/Si3211 Register 64. Linefeed Control Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7 Reserved Read returns zero. 6:4 LFS[2:0] Linefeed Shadow. This register reflects the actual real-time linefeed state. Automatic operations may cause actual linefeed state ...

Page 95

Register 65. External Bipolar Transistor Control Bit D7 D6 Name SQH Type R/W Reset settings = 0110_0001 Bit Name 7 Reserved Read returns zero. 6 SQH Audio Squelch squelch STIPAC and SRINGAC pins squelched. 5 ...

Page 96

Si3210/Si3211 Register 66. Battery Feed Control Bit D7 D6 Name Type Reset settings = 0000_0011 Bit D7 D6 Name Type Reset settings = 0000_0110 Bit Name 7:5 Reserved Read returns zero. 4 VOV Overhead Voltage Range Increase. (Si3210 only; See ...

Page 97

Register 67. Automatic/Manual Control Bit D7 D6 Name MNCM Type R/W Reset settings = 0001_1111 Bit Name 7 Reserved Read returns zero. 6 MNCM Common Mode Manual/Automatic Select Automatic control Manual control, in which TIP (forward) ...

Page 98

Si3210/Si3211 Register 68. Loop Closure/Ring Trip Detect Status Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:3 Reserved Read returns zero. 2 DBIRAW Ring Trip/Loop Closure Unfiltered Output. State of this bit reflects the real-time output of ...

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Register 70. Ring Trip Detect Debounce Interval Bit D7 D6 Name Type Reset settings = 0000_1010 Bit Name 7 Reserved Read returns zero. 6:0 RTDI[6:0] Ring Trip Detect Debounce Interval. The value written to this register defines the minimum steady ...

Page 100

Si3210/Si3211 Register 72. On-Hook Line Voltage Bit D7 D6 Name VSGN Type R/W Reset settings = 0010_0000 Bit Name 7 Reserved Read returns zero. 6 VSGN On-Hook Line Voltage. The value written to this bit sets the on-hook line voltage ...

Page 101

Register 74. High Battery Voltage Bit D7 D6 Name Type Reset settings = 0011_0010 Bit Name 7:6 Reserved Read returns zero. 5:0 VBATH[5:0] High Battery Voltage. The value written to this register sets high battery voltage. V equal to VBATL. ...

Page 102

Si3210/Si3211 Register 76. Power Monitor Pointer Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:3 Reserved Read returns zero. 2:0 PWRMP[2:0] Power Monitor Pointer. Selects the external transistor from which to read power output. The power of ...

Page 103

Register 78. Loop Voltage Sense Bit D7 D6 Name LVSP Type R Reset settings = 0000_0000 Bit Name 7 Reserved Read returns zero. 6 LVSP Loop Voltage Sense Polarity. This register reports the polarity of the differential loop voltage (V ...

Page 104

Si3210/Si3211 Register 80. TIP Voltage Sense Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 VTIP[7:0] TIP Voltage Sense. This register reports the real-time voltage at TIP with respect to ground. The range (0x00) ...

Page 105

Register 83. Battery Voltage Sense 2 Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 VBATS2[7:0] Battery Voltage Sense 2. This register is one of two registers that reports the real-time voltage ground. The ...

Page 106

Si3210/Si3211 Register 86. Transistor 3 Current Sense Bit D7 D6 Name Type Reset settings = xxxx_xxxx Bit Name 7:0 IQ3[7:0] Transistor 3 Current Sense. This register reports the real-time current through Q3. The range (0x00) to 9.59 ...

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Register 89. Transistor 6 Current Sense Bit D7 D6 Name Type Reset settings = xxxx_xxxx Bit Name 7:0 IQ6[7:0] Transistor 6 Current Sense. This register reports the real-time current through Q6. The range (0x00) to 80.58 mA ...

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Si3210/Si3211 Register 93. DC-DC Converter Switching Delay Bit D7 D6 Name DCCAL Type R/W Reset settings = 0001_0100 (Si3210) Reset settings = 0011_0100 (Si3210M) Bit D7 D6 Name Type Reset settings = xxxx_xxxx Bit Name 7 DCCAL DC-DC Converter Peak ...

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Register 94. DC-DC Converter PWM Pulse Width Bit D7 D6 Name Type Reset settings = 0000_0000 Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 DCPW[7:0] DC-DC Converter Pulse Width (Si3210 only). Pulse width of DCDRV is ...

Page 110

... Calibration enabled or in progress. 3 CALT TIP Gain Mismatch Calibration. For use with discrete solution only. When using the Si3201, consult “AN35: Si321x User’s Quick Reference Guide” and follow instructions for manual calibration Normal operation or calibration complete Calibration enabled or in progress. ...

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Register 97. Calibration Control/Status Register 2 Bit D7 D6 Name Type Reset settings = 0001_1111 Bit Name 7:5 Reserved Read returns zero. 4 CALM1 Monitor ADC Calibration Normal operation or calibration complete Calibration enabled or ...

Page 112

Si3210/Si3211 Register 99. TIP Gain Mismatch Calibration Result Bit D7 D6 Name Type Reset settings = 0001_0000 Bit Name 7:5 Reserved Read returns zero. 4:0 CALGMT[4:0] Gain Mismatch of IE Tracking Loop for TIP Current. Register 100. Differential Loop Current ...

Page 113

Register 102. Current Limit Calibration Result Bit D7 D6 Name Type Reset settings = 0000_1000 Bit Name 7:5 Reserved Read returns zero. 3:0 CALGIL[3:0] Current Limit Calibration Result. Register 103. Monitor ADC Offset Calibration Result Bit D7 D6 Name CALMG1[3:0] ...

Page 114

Si3210/Si3211 Register 105. DAC Offset Calibration Result Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 DACOF[7:0] DAC Offset Calibration Result. Register 106. Common Mode Balance Calibration Result Bit D7 D6 Name Type Reset settings = 0010_0000 ...

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Register 108. Enhancement Enable Note: The Enhancement Enable register and associated features are available in silicon revisions C and later. Bit D7 D6 Name ILIMEN FSKEN Type R/W R/W Reset settings = 0000_0000 Bit D7 D6 Name ILIMEN FSKEN Type ...

Page 116

Si3210/Si3211 Bit Name 4 ZSEXT Impedance Internal Reference Resistor Disable. When enabled, this bit removes the internal reference resistor used to synthesize ac impedances for 600 + 2.1 µF and 900 + 2.16 µF so that an external resistor reference ...

Page 117

Indirect Registers Indirect registers are not directly mapped into memory but are accessible through the IDA and IAA registers. A write to IDA followed by a write to IAA is interpreted as a write request to an indirect register. ...

Page 118

Si3210/Si3211 Table 38. DTMF Indirect Registers Description Addr. 0 DTMF Row 0 Peak Magnitude Pass Ratio Threshold. This register sets the minimum power ratio threshold for row 0 DTMF detection. If the ratio of power in row 0 to total ...

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Oscillators See functional description sections of tone generation, ringing, and pulse metering for guidelines on computing register values. All values are represented in 2s- complement format. Note: The values of all indirect registers are undefined follow- ing the reset ...

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Si3210/Si3211 Table 40. Oscillator Indirect Registers Description Addr. Oscillator 1 Frequency Coefficient. 13 Sets tone generator 1 frequency. Oscillator 1 Amplitude Register. 14 Sets tone generator 1 signal amplitude. Oscillator 1 Initial Phase Register. 15 Sets initial phase of tone ...

Page 121

Digital Programmable Gain/Attenua- tion See functional description sections programmable gain/attenuation for computing register values. All values are represented in 2s-complement format. Note: The values of all indirect registers are undefined follow- ing the reset state. Shaded areas denote bits ...

Page 122

Si3210/Si3211 4.4. SLIC Control See descriptions of linefeed interface and power monitoring for guidelines on computing register values. All values are represented in 2s-complement format. Note: The values of all indirect registers are undefined follow- ing the reset state. Shaded ...

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Table 44. SLIC Control Indirect Registers Description Addr. 28 Loop Closure Threshold. Loop closure detection threshold. This register defines the upper bounds threshold if hys- teresis is enabled (direct Register 108, bit 0). The range is 0– 1.27 ...

Page 124

Si3210/Si3211 4.5. FSK Control For detailed instructions on FSK signal generation, refer to “Application Note 32: FSK Generation” (AN32). These registers support enhanced FSK generation mode, which is enabled by setting FSKEN = 1 (direct Register 108, bit 6) and ...

Page 125

Pin Descriptions: Si3210/11 QFN DTX FSYNC 2 RESET 3 SDCH/DIO1 4 SDCL/DIO2 DDA1 IREF 7 CAPP 8 QGND 9 CAPM 10 STIPDC 11 SRINGDC ...

Page 126

Si3210/Si3211 QFN TSSOP Name Pin # Pin # 5 9 SDCL/DIO2 6 10 VDDA1 7 11 IREF 8 12 CAPP 9 13 QGND 10 14 CAPM 11 15 STIPDC 12 16 SRINGDC 13 17 STIPE 14 18 SVBAT 15 19 ...

Page 127

QFN TSSOP Name Pin # Pin # 23 27 VDDA2 Analog Supply Voltage. Analog power supply for internal analog circuitry ITIPP Positive TIP Current Control. Analog current output driving Q1 ITIPN Negative TIP Current Control. Analog ...

Page 128

... Si3210/Si3211 6. Pin Descriptions: Si3201 Pin # Name Input/ Output 1 TIP I — 3 RING I/O 4 VBAT — 5 VBATH — 7 GND — 8 VDD — 10 SRINGE O 11 STIPE O 13 IRINGN I 14 IRINGP I 15 ITIPN I 16 ITIPP I Bottom-Side — Exposed Pad 128 TIP 1 16 ITIPP ITIPN RING ...

Page 129

... ProSLIC Si3211-KT ProSLIC Si3211-BT ProSLIC Si3211-E-FT ProSLIC Si3211-E-GT ProSLIC Si3211-E-FM ProSLIC Si3211-E-GM ProSLIC Si3201-KS Linefeed Interface Si3201-BS Linefeed Interface Si3201-FS Linefeed Interface Si3201-GS Linefeed Interface Note: Add an “R” at the end of the device to denote tape and reel; 2500 quantity per reel. ...

Page 130

... Si3210-QFN Eval Board, Daughter Card Si3210-TSSOP Eval Board, Daughter Card Si3210-TSSOP Eval Board, Daughter Card Si3210M-TSSOP Eval Board, Daughter Card Si3210M-TSSOP Eval Board, Daughter Card Si3211-TSSOP Eval Board, Daughter Card Rev. 1.45 Linefeed Interface Discrete Si3201 Discrete Si3201 Discrete Si3201 Discrete ...

Page 131

Package Outline: 38-Pin QFN Figure 33 illustrates the package details for the Si321x. Table 48 lists the values for the dimensions shown in the illustration. Figure 33. 38-Pin Quad Flat No-Lead Package (QFN) Table 48. Package Diagram Dimensions Symbol ...

Page 132

Si3210/Si3211 9. Package Outline: 38-Pin TSSOP Figure 34 illustrates the package details for the Si321x. Table 49 lists the values for the dimensions shown in the illustration. Figure 34. 38-Pin Thin Shrink Small Outline Package (TSSOP) Table 49. Package Diagram ...

Page 133

... Package Outline: 16-Pin ESOIC Figure 35 illustrates the package details for the Si3201. Table 50 lists the values for the dimensions shown in the illustration. Figure 35. 16-Pin Thermal Enhanced Small Outline Integrated Circuit (ESOIC) Package Si3210/Si3211 Rev. 1.45 133 ...

Page 134

Si3210/Si3211 Table 50. Package Diagram Dimensions Symbol aaa bbb ccc ddd 134 Millimeters Min A — A1 0.00 A2 1.25 b 0.31 c 0.17 D 9.90 BSC D1 3.45 E 6.00 BSC E1 3.90 BSC E2 2.20 e 1.27 BSC ...

Page 135

... RoHS-  Compliant”  Figure 9, “Si3210/Si3210M Application Circuit Using Si3201,” on page 17. Added additional decoupling components to VDDA1,  VDDA2, and VDDD.  Figure 12, “Si3211 Typical Application Circuit Using Si3201,” on page 22. ...

Page 136

Si3210/Si3211 Added Note 1.   Updated Table 16. Changed current rating 150 mA.  Corrected missing reference to R5.  Added new row for R26 and changed the value to  10 k. Added title for ...

Page 137

N : OTES Si3210/Si3211 Rev. 1.45 137 ...

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... Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap- plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories, Silicon Labs, and ProSLIC are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. ...

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