SI3201-FSR Silicon Laboratories Inc, SI3201-FSR Datasheet - Page 39

• Manufacturer Part Number: SI3201-FSR
• Description: SLIC 1-CH 60dB 41mA 3.3V/5V 16-Pin SOIC EP T/R
• Manufacturer: Silicon Laboratories Inc

Specifications of SI3201-FSR

• Package: 16SOIC EP
• Number Of Channels Per Chip: 1
• Longitudinal Balanced: 60 dB
• Loop Current: 41 mA
• Minimum Operating Supply Voltage: 3.13 V
• Typical Operating Supply Voltage: 3.3|5 V
• Typical Supply Current: 88 mA

2.3.4. Enhanced FSK Waveform Generation
Enhanced FSK generation capabilities can be enabled
by setting FSKEN = 1 (direct Register 108, bit 6) and
REN = 1 (direct Register 32, bit 6). In this mode, the
user can define mark (1) and space (0) attributes once
during initialization by defining indirect Registers 69–74.
The user need only indicate 0-to-1 and 1-to-0 transitions
in the information stream. By writing to FSKDAT (direct
Register 52), this mode applies a 24 kHz sample rate to
tone generator 1 to give additional resolution to timers
and frequency generation. “AN32: Si321x Frequency
Shift
instructions on how to implement FSK in this mode.
Additionally, sample source code is available from
Silicon Laboratories upon request.
2.3.5. Tone Generator Interrupts
Both the active and inactive timers can generate their
own interrupt to signal “on/off” transitions to the
software. The timer interrupts for tone generator 1 can
be individually enabled by setting the O1AE and O1IE
bits (direct Register 21, bits 0 and 1, respectively).
Timer interrupts for tone generator 2 are O2AE and
O2IE (direct Register 21, bits 2 and 3, respectively). A
pending interrupt for each of the timers is determined by
reading the O1AP, O1IP, O2AP, and O2IP bits in the
Interrupt Status 1 register (direct Register 18, bits 0
through 3, respectively).
2.4. Ringing Generation
The ProSLIC provides fully-programmable internal
balanced ringing with or without a dc offset to ring a
wide variety of terminal devices. All parameters
associated with ringing are software-programmable:
ringing frequency, waveform, amplitude, dc offset, and
ringing cadence. Both sinusoidal and trapezoidal ringing
waveforms are supported, and the trapezoidal crest
factor is programmable. Ringing signals of up to 90 V
peak or more can be generated, enabling the ProSLIC
to drive a 5 REN (1380  + 40 µF) ringer load across
loop lengths of 2000 feet (160  ) or more.
Keying
(FSK)
Modulation”
gives
detailed
Rev. 1.0
2.4.1. Ringing Architecture
The ringing generator architecture is nearly identical to
that of the tone generator. The sinusoid ringing
waveform is generated using an internal two-pole
resonance
frequency and amplitude. However, since ringing
frequencies are very low compared to the audio band
signaling
generated at a 1 kHz rate instead of 8 kHz.
The ringing generator has two timers that function the
same as for the tone generator timers. They allow on/off
cadence settings up to 8 seconds on/ 8 seconds off. In
addition to controlling ringing cadence, these timers
control the transition into and out of the Ringing state.
Table 29 summarizes the list of registers used for
ringing generation.
Note: Tone generator 2 should not be enabled concurrently
When the Ringing state is invoked by writing
LF[2:0] = 100 (direct Register 64), the ProSLIC goes
into the Ringing state and starts the first ring. At the
expiration of RAT, the ProSLIC turns off the ringing
waveform and goes to the on-hook transmission state.
Upon expiration of RIT, ringing again initiates. This
process continues as long as the two timers are
enabled and the Linefeed Control register is set to the
Ringing state.
with the ringing generator due to resource sharing
within the hardware.
frequencies,
oscillator
circuit
the
ringing
with
Si3216
programmable
waveform
39
is