SI3200-G-GS Silicon Laboratories Inc, SI3200-G-GS Datasheet - Page 94

• Manufacturer Part Number: SI3200-G-GS
• Description: SLIC 2-CH 63dB 45mA 3.3V 6-Pin SMD
• Manufacturer: Silicon Laboratories Inc
• Series: ProSLIC®r

Specifications of SI3200-G-GS

• Package: 6SMD
• Number Of Channels Per Chip: 2
• Polarity Reversal: Yes
• Longitudinal Balanced: 63 dB
• Loop Current: 45 mA
• Minimum Operating Supply Voltage: 3.13 V
• Typical Operating Supply Voltage: 3.3 V
• Typical Supply Current: 0.11 mA
• Function: Subscriber Line Interface Concept (SLIC), CODEC
• Interface: GCI, PCM, SPI
• Number Of Circuits: 2
• Voltage - Supply: 3.3V, 5V
• Current - Supply: 110µA
• Power (watts): 941mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (3.9mm Width)
• Includes: Battery Switching, BORSCHT Functions, DTMF Generation and Decoding, FSK Tone Generation, Modem and Fax Tone Detection
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Si3232
BSWLPF: RING Voltage Filter Coefficient (RAM Address 33)
Reset settings = 0x00
CMHITH: Speedup Threshold—High Byte (RAM Address 36)
Reset settings = 0x00
CMLOTH: Speedup Threshold—Low Byte (RAM Address 35)
Reset settings = 0x00
94
15:3
15:0
15:0
Name
Name
Name
Type
Type
Type
Bit
Bit
Bit
Bit
Bit
Bit
D15
D15
D15
CMLOTH[15:0]
BSWLPF[15:3]
CMHITH[15:0]
Name
Name
Name
D14
D14
D14
D13
D13
D13
RING Voltage Filter Coefficient.
Programs the digital low-pass filter block that filters the voltage measured on the
RING lead used to determine battery switching threshold.
Speedup Threshold—High Byte.
Programs the upper byte of the threshold at which speedup mode in enabled. The
CMLOTH RAM location holds the lower byte of this value.
Speedup Threshold—Low Byte.
Programs the lower byte of the threshold at which speedup mode in enabled. The
CMHITH RAM location holds the upper byte of this value.
D12
D12
D12
D11
D11
D11
D10
D10
D10
BSWLPF[15:3]
Preliminary Rev. 0.96
R/W
D9
D9
D9
CMLOTH[15:0]
CMHITH[15:0]
D8
D8
D8
R/W
R/W
D7
D7
D7
Function
Function
Function
D6
D6
D6
D5
D5
D5
D4
D4
D4
D3
D3
D3
D2
D2
D2
D1
D1
D1
D0
D0
D0