S19233PBIFB AMCC, S19233PBIFB Datasheet - Page 13

• Manufacturer Part Number: S19233PBIFB
• Description: Ethernet/Fibre Channel 49-Pin BGA
• Manufacturer: AMCC

Specifications of S19233PBIFB

• Package: 49BGA
• Maximum Data Rate: 11.32 Gbps
• Transmission Media Type: Wire
• Power Supply Type: Analog
• Typical Supply Current: 380 mA
• Typical Operating Supply Voltage: 1.8|3.3 V
• Minimum Operating Supply Voltage: 1.65|3.03 V
• Maximum Operating Supply Voltage: 1.95|3.56 V

S19233 – 10 G Ethernet/Fibre Channel/SONET/SDH
Dual CDR
I2C BUS
S19233 uses a simple bi-directional two-wire bus for
efficient inter-IC control. All register controlled features
and functions are programmed via the I
11summarizes the register map and description nec-
e s s a r y f o r p r o p e r o p e r a t i o n . A m o r e d e ta i l e d
description can found in the S19233 Programmer’s
Reference Manual, PRM2001.
The following are some important features of I
The serial port interface is based on the I
nication occurs across two wires and is formatted in
frames. The two wires are clock (SCL) and data
(SDA). At the rising edge of RSTB, the S19233 loads
t h e d e v i c e a d d r e s s i n t o a r e g i s t e r f r o m t h e
DEVICE_ADDR[6:0] and uses it to decode accesses
Figure 3. Two Wire Slave Address
AMCC Confidential and Proprietary
•
•
The S19233 has a unique address on the bus
and a slave configuration at all times.
Only two bus lines are required; a serial Data
Input/Output line (SDA) and a Clock line (SCL).
®
and Address Register
MSB
1
0
7-bit slave address
1
2
C. Commu-
2
C. Table
2
C bus:
0
0
to its registers. The DEVICE_ADDR[6:0] default is
fixed at 51h. The address bits are used to uniquely
identify the S19233 device if multiple I
controlled by a single microprocessor. A more detailed
I
Interface Application Note, AN2076.
A frame is formatted as shown in Figure 3.
I
during SCL high time.
I
the receiver after a data transfer.
I
the receiver after a data transfer.
Stop Code:
After this condition, the bus becomes tristated, and both
SDA and SCL are pulled high.
REFCLKP/N must be supplied continuously in order to
access read/write registers through the I
2
2
2
2
C Not Acknowledge: A high left on the SDA line by
C interface description can found in the S19233 I
C Start/Repeat Conditions: A falling edge on SDA
C Acknowledge:
0
A rising edge on SDA during SCL high time.
1
A low assertion on the SDA line from
Revision 5.00 – March 16, 2007
W=0
LSB ACK
R/W
R=1
Data Sheet
2
C devices are
2
C interface.
2
13
C