SCC2681AC1N28 NXP Semiconductors, SCC2681AC1N28 Datasheet - Page 19

• Manufacturer Part Number: SCC2681AC1N28
• Description: UART 2-CH 5V 28-Pin PDIP Tube
• Manufacturer: NXP Semiconductors

Specifications of SCC2681AC1N28

• Package: 28PDIP
• Number Of Channels Per Chip: 2
• Maximum Data Rate: 0.1152 MBd
• Transmitter And Receiver Fifo Counter: No
• Operating Supply Voltage: 5 V
• Minimum Single Supply Voltage: 4.75 V
• Maximum Processing Temperature: 260 °C
• Maximum Supply Current: 10 mA

has no effect on the INTRN output. Note that the IMR does not mask
Philips Semiconductors
ISR – Interrupt Status Register
This register provides the status of all potential interrupt sources.
The contents of this register are masked by the Interrupt Mask
Register (IMR). If a bit in the ISR is a ‘1’ and the corresponding bit in
the IMR is also a ‘1’, the INTRN output will be asserted. If the
corresponding bit in the IMR is a zero, the state of the bit in the ISR
the reading of the ISR – the true status will be provided regardless
of the contents of the IMR. The contents of this register are
initialized to 00
ISR[7] – Input Port Change Status
This bit is a ‘1’ when a change-of-state has occurred at the IP0, IP1,
IP2, or IP3 inputs and that event has been selected to cause an
interrupt by the programming of ACR[3:0]. The bit is cleared when
the CPU reads the IPCR.
ISR[6] – Channel B Change In Break
This bit, when set, indicates that the Channel B receiver has
detected the beginning or the end of a received break. It is reset
when the CPU issues a Channel B ‘reset break change interrupt’
command.
ISR[5] – Channel B Receiver Ready or FIFO Full
The function of this bit is programmed by MR1B[6]. If programmed
as receiver ready, it indicates that a character has been received in
Channel B and is waiting in the FIFO to be read by the CPU. It is set
when the character is transferred from the receive shift register to
the FIFO and reset when the CPU reads the RHR. If after this read
there are more characters still in the FIFO the bit will be set again
after the FIFO is ‘popped’. If programmed as FIFO full, it is set when
a character is transferred from the receive holding register to the
receive FIFO and the transfer caused the Channel B FIFO to
become full; i.e., all three FIFO positions are occupied. It is reset
when the CPU reads the RHR. If a character is waiting in the
receive shift register because the FIFO is full, the bit will be set
again when the waiting character is loaded into the FIFO.
ISR[4] – Channel B Transmitter Ready
This bit is a duplicate of TxRDYB (SRB[2]).
ISR[3] – Counter Ready
In the counter mode, this bit is set when the counter reaches
terminal count and is reset when the counter is stopped by a stop
counter command.
In the timer mode, this bit is set once each cycle of the generated
square wave (every other time that the counter/timer reaches zero
count). The bit is reset by a stop counter command. The command,
however, does not stop the counter/timer.
ISR[2] – Channel A Change in Break
This bit, when set, indicates that the Channel A receiver has
detected the beginning or the end of a received break. It is reset
when the CPU issues a Channel A ‘reset break change interrupt’
command.
ISR[1] – Channel A Receiver Ready Or FIFO Full
The function of this bit is programmed by MR1A[6]. If programmed
as receiver ready, it indicates that a character has been received in
Channel A and is waiting in the FIFO to be read by the CPU. It is set
when the character is transferred from the receive shift register to
the FIFO and reset when the CPU read the RHR. IF after this read
there are more characters still in the FIFO the bit will be set again
after the FIFO is ‘popped’. If programmed as FIFO full, it is set when
a character is transferred from the receive holding register to the
receive FIFO and the transfer caused the Channel A FIFO to
2004 Apr 06
Dual asynchronous receiver/transmitter (DUART)
16
when the DUART is reset.
19
square wave with a period of twice the value (in clock periods) of the
the C/T runs continuously. Receipt of a start counter command (read
communicating may also have a small error in the precise baud rate.
become full; i.e., all three FIFO positions are occupied. It is reset
when the CPU reads the RHR. If a character is waiting in the
receive shift register because the FIFO is full, the bit will be set
again when the ISR[0] and IMR waiting character is loaded into the
FIFO.
ISR[0] – Channel A Transmitter Ready
This bit is a duplicate of TxRDYA (SRA[2]).
IMR – Interrupt Mask Register
The programming of this register selects which bits in the ISR
causes an interrupt output. If a bit in the ISR is a ‘1’ and the
corresponding bit in the IMR is also a ‘1’ the INTRN output will be
asserted. If the corresponding bit in the IMR is a zero, the state of
the bit in the ISR has no effect on the INTRN output. Note that the
IMR does not mask the programmable interrupt outputs OP3–OP7
or the reading of the ISR.
CTUR and CTLR – Counter/Timer Registers
The CTUR and CTLR hold the eight MSBs and eight LSBs,
respectively, of the value to be used by the counter/timer in either
the counter or timer modes of operation. The minimum value which
may be loaded into the CTUR/CTLR registers is 0x0002. Note that
these registers are write-only and cannot be read by the CPU.
In the timer (programmable divider) mode, the CT generates a
CTUR and CTLR.
If the value in CTUR and CTLR is changed, the current half-period
will not be affected, but subsequent half periods will be. In this mode
with A3-A0 = 1110) causes the counter to terminate the current
timing cycle and to begin a new cycle using the values in CTUR and
CTLR. The waveform so generated is often used for a data clock.
The formula for calculating the divisor n to load to the CTUR and
CTLR for a particular 1 data clock is shown below:
Often this division will result in a non-integer number; 26.3, for
example. One can only program integer numbers in a digital divider.
Therefore, 26 would be chosen. This gives a baud rate error of
0.3/26.3 which is 1.14%; well within the ability asynchronous mode
of operation.
One should be cautious about the assumed benign effects of small
errors since the other receiver or transmitter with which one is
In a ‘clean’ communications environment using one start bit, eight
data bits and one stop bit the total difference allowed between the
transmitter and receiver frequency is approximately 4.6%. Less than
eight data bits will increase this percentage.
The counter ready status bit (ISR[3]) is set once each cycle of the
square wave. The bit is reset by a stop counter command (read with
A3-A0 = 1111). The command however, does not stop the C/T. The
generated square wave is output on OP3 if it is programmed to be
the C/T output.
On power up and after reset the timer/counter comes up stopped
and in the timer mode. It will require a start counter command (a
read at address 0xE) to start it. Because it cannot be shut off or
stopped once started, and runs continuously in timer mode, it is
recommended that at initialization, the output port (OP3) should be
n
16
counter clock frequency
2
baud rate desired
SCC2681
Product data