ATF-551M4-BLK Avago Technologies US Inc., ATF-551M4-BLK Datasheet - Page 20

• Manufacturer Part Number: ATF-551M4-BLK
• Description: IC PHEMT 2GHZ 2.7V 10MA MINIPAK
• Manufacturer: Avago Technologies US Inc.

Specifications of ATF-551M4-BLK

• Package / Case: 4-MiniPak (1412)
• Mfg Application Notes: ATF-541M4 AppNote
• Transistor Type: pHEMT FET
• Frequency: 2GHz
• Gain: 17.5dB
• Voltage - Rated: 5V
• Current Rating: 100mA
• Noise Figure: 0.5dB
• Current - Test: 10mA
• Voltage - Test: 2.7V
• Power - Output: 14.6dBm
• Configuration: Single Dual Source
• Transistor Polarity: N-Channel
• Power Dissipation: 270 mW
• Drain Source Voltage Vds: 5 V
• Gate-source Breakdown Voltage: - 5 V to 1 V
• Continuous Drain Current: 100 mA
• Maximum Operating Temperature: + 150 C
• Maximum Drain Gate Voltage: - 5 V to 1 V
• Minimum Operating Temperature: - 65 C
• Mounting Style: SMD/SMT
• Channel Type: N
• Drain-gate Voltage (max): -5 to 1V
• Operating Temperature (max): 150C
• Operating Temperature Classification: Military
• Mounting: Surface Mount
• Pin Count: 4
• Continuous Drain Current Id: 100mA
• Power Dissipation Pd: 270mW
• Noise Figure Typ: 0.5dB
• Rf Transistor Case: MiniPak
• No. Of Pins: 4
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

V
V
I
I
voltage divider network.
The value of resistors R1 and R2 are calculated with the
following formulas.
Example Circuit
V
V
I
V
Choose I
gate leakage current. I
be 0.5 mA for this example. Using equations (1), (2), and
(3) the resistors are calculated as follows
R1 = 940Ω
R2 = 4460Ω
R3 = 28.6Ω
Active Biasing
Active biasing provides a means of keeping the
quiescent bias point constant over temperature and
constant over lot to lot variations in device dc perfor-
mance. The advantage of the active biasing of an en-
hancement mode PHEMT versus a depletion mode
PHEMT is that a negative power source is not required.
Figure . Typical ATF-551M4 LNA with Active Biasing.
The techniques of active biasing an enhancement mode
device are very similar to those used to bias a bipolar
junction transistor.
INPUT
20
ds
BB
R1 =
R2 = (V
ds
ds
ds
DD
DD
gs
= 10 mA
is the desired drain current.
= 2.7V
= 0.47V
is the device drain to source voltage.
is the current flowing through the R1/R2 resistor
= 3V
is the power supply voltage.
Zo
V
I
R7
BB
gs
R5
R6
C1
ds
p
L1
BB
– V
R1
gs
C3
to be at least 10X the maximum expected
C2
gs
) R1
Q1
L2
C7
Q2
L3
R2
BB
L4
R4
C5
C6
was conservatively chosen to
(2)
(3)
(3)
C4
R3
Zo
OUTPUT
Vdd
An active bias scheme is shown in Figure 38.
R1 and R2 provide a constant voltage source at the
base of a PNP transistor at Q2. The constant voltage
at the base of Q2 is raised by 0.7 volts at the emitter.
The constant emitter voltage plus the regulated V
supply are present across resistor R3. Constant voltage
across R3 provides a constant current supply for the
drain current. Resistors R1 and R2 are used to set the
desired V
also sets the amount of extra current consumed by the
bias network. The equations that describe the circuit’s
operation are as follows.
Rearranging equation (4)provides the following formula
and rearranging equation (5) provides the follow
formula
Example Circuit
V
V
I
R4 = 10Ω
V
Equation (1) calculates the required voltage at the
emitter of the PNP transistor based on desired V
I
lates the value of resistor R3 which determines the drain
current I
lates the voltage required at the junction of resistors R1
and R2. This voltage plus the step-up of the base emitter
junction determines the regulated V
(5) are solved simultaneously to determine the value of
resistors R1 and R2. In the example R1=4200Ω and R2
=1800Ω.
ds
ds
V
R3 = V
V
V
V
R2 =
R1 =
ds
DD
BE
E
B
B
DD
= 10 mA
through resistor R4 to be 2.8V. Equation (2) calcu-
= V
= V
=
= 2.7 V
= 0.7 V
= 3 V
= I
ds
R1 + R2
I
E
R
BB
BB
DD
– V
1
+ (I
ds
I
R1
(
(R1 + R2)
ds
(V
ds
– V
. In the example R3=18.2Ω. Equation (3) calcu-
V
1 +
. The combined series value of these resistors
BE
ds
DD
B
E
p
•
p
– V
V
R4)
V
V
DD
DD
DD
B
V
)
p
– V
B
(4)
(5)
(3)
(4A)
(1)
(2)
B
p
)
9
(5A)
ds
. Equations (4) and
ds
and
DD