MT47H32M16HR-3 IT:F TR Micron Technology Inc, MT47H32M16HR-3 IT:F TR Datasheet - Page 12

• Manufacturer Part Number: MT47H32M16HR-3 IT:F TR
• Description: DRAM Chip DDR2 SDRAM 512M-Bit 32Mx16 1.8V 84-Pin FBGA T/R
• Manufacturer: Micron Technology Inc
• Type: DDR2 SDRAMr

Specifications of MT47H32M16HR-3 IT:F TR

• Density: 512 Mb
• Maximum Clock Rate: 667 MHz
• Package: 84FBGA
• Address Bus Width: 15 Bit
• Operating Supply Voltage: 1.8 V
• Maximum Random Access Time: 0.45 ns
• Operating Temperature: -40 to 85 °C
• Organization: 32Mx16
• Address Bus: 15b
• Access Time (max): 450ps
• Operating Supply Voltage (typ): 1.8V
• Package Type: FBGA
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 250mA
• Pin Count: 84
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Compliant

Functional Block Diagrams
Figure 3: 128 Meg x 4 Functional Block Diagram
PDF: 09005aef82f1e6e2
512MbDDR2.pdf - Rev. R 12/10 EN
BA0, BA1
A0–A13,
RAS#
CAS#
ODT
WE#
CKE
CK#
CS#
CK
16
Address
register
registers
Control
Mode
logic
16
counter
Refresh
14
11
2
The DDR2 SDRAM is a high-speed CMOS, dynamic random access memory. It is inter-
nally configured as a multibank DRAM.
14
address
2
Row-
MUX
Column-
counter/
control
address
Bank
logic
latch
14
latch and
decoder
address
Bank0
row-
Bank1
Bank2
Bank3
9
2
16,384
DM mask logic
(16,384 x 512 x 16)
Sense amplifiers
I/O gating
decoder
Column
8,192
Memory
Bank1
Bank0
array
(x16)
Bank2
512
Bank3
COL0, COL1
internal
CK, CK#
16
12
16
16
Read
latch
CK out
drivers
Write
FIFO
CK in
and
4
4
4
4
Micron Technology, Inc. reserves the right to change products or specifications without notice.
COL0, COL1
Mask
Data
MUX
16
4
generator
512Mb: x4, x8, x16 DDR2 SDRAM
DQS
1
1
1
1
4
4
4
4
registers
Input
Data
4
1
1
1
1
4
4
4
4
DQS, DQS#
2
Functional Block Diagrams
1
4
CK, CK#
DRVRS
2
DLL
RCVRS
© 2004 Micron Technology, Inc. All rights reserved.
sw1 sw2
sw1 sw2
sw1 sw2
sw1 sw2
R1
R1
R1
R1
R1
R1
ODT control
R2
R2
R2
R2
R2
R2
VssQ
sw3
sw3
sw3
sw3
R3
R3
R3
R3
R3
R3
VddQ
DM
DQ0–DQ3
DQS, DQS#