MT48H16M16LFBF-75:H TR Micron Technology Inc, MT48H16M16LFBF-75:H TR Datasheet - Page 52
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MT48H16M16LFBF-75:H TR
Manufacturer Part Number
MT48H16M16LFBF-75:H TR
Description
DRAM Chip Mobile SDRAM 256M-Bit 16Mx16 1.8V 54-Pin VFBGA T/R
Manufacturer
Micron Technology Inc
Type
Mobile SDRAMr
Datasheet
1.MT48H8M32LFB5-6H.pdf
(86 pages)
Specifications of MT48H16M16LFBF-75:H TR
Package
54VFBGA
Density
256 Mb
Address Bus Width
15 Bit
Operating Supply Voltage
1.8 V
Maximum Clock Rate
133 MHz
Maximum Random Access Time
8|6 ns
Operating Temperature
0 to 70 °C
- Current page: 52 of 86
- Download datasheet (3Mb)
Figure 22: Terminating a READ Burst
PDF: 09005aef834c13d2
256mb_mobile_sdram_y36n.pdf - Rev. I 11/09 EN
Note:
Continuous-page READ bursts can be truncated with a BURST TERMINATE command
and fixed-length READ bursts can be truncated with a BURST TERMINATE command,
provided that auto precharge was not activated. The BURST TERMINATE command
should be issued x cycles before the clock edge at which the last desired data element is
valid, where x = CL - 1. This is shown in Figure 22 (page 52) for each possible CAS
latency; data element n + 3 is the last desired data element of a longer burst.
Command
Command
1. DQM is LOW.
Address
Address
CLK
CLK
DQ
DQ
Bank,
T0
Col n
T0
READ
Bank,
READ
Col n
CL = 2
CL = 3
T1
T1
256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM
NOP
NOP
52
T2
T2
NOP
NOP
D
OUT
Micron Technology, Inc. reserves the right to change products or specifications without notice.
T3
T3
NOP
NOP
D
D
OUT
OUT
TERMINATE
TERMINATE
BURST
BURST
T4
T4
X = 1 cycle
D
D
OUT
OUT
Transitioning data
X = 2 cycles
T5
T5
NOP
NOP
D
D
OUT
OUT
©2008 Micron Technology, Inc. All rights reserved.
T6
T6
READ Operation
NOP
NOP
D
OUT
Don’t Care
T7
NOP
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