MT48LC16M16A2BG-7E:D Micron Technology Inc, MT48LC16M16A2BG-7E:D Datasheet - Page 64

• Manufacturer Part Number: MT48LC16M16A2BG-7E:D
• Description: DRAM Chip SDRAM 256M-Bit 16Mx16 3.3V 54-Pin VFBGA Tray
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48LC16M16A2BG-7E:D

• Package: 54VFBGA
• Density: 256 Mb
• Address Bus Width: 15 Bit
• Operating Supply Voltage: 3.3 V
• Maximum Clock Rate: 143 MHz
• Maximum Random Access Time: 5.4 ns
• Operating Temperature: 0 to 70 °C
• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 256M (16Mx16)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 54-VFBGA
• Organization: 16Mx16
• Address Bus: 15b
• Access Time (max): 5.4ns
• Operating Supply Voltage (typ): 3.3V
• Package Type: VFBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 135mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 34: WRITE-to-PRECHARGE
PDF: 09005aef8091e6d1
256Mb_sdr.pdf - Rev. N 1/10 EN
Note:
Fixed-length WRITE bursts can be truncated with the BURST TERMINATE command.
When truncating a WRITE burst, the input data applied coincident with the BURST TER-
MINATE command is ignored. The last data written (provided that DQM is LOW at that
time) will be the input data applied one clock previous to the BURST TERMINATE com-
mand. This is shown in Figure 35 (page 65), where data n is the last desired data
element of a longer burst.
t
t
Command
Command
WR @
WR @
1. In this example DQM could remain LOW if the WRITE burst is a fixed length of two.
Address
Address
DQM
DQM
CLK
t
t
DQ
DQ
CK
CK < 15ns
15ns
WRITE
Bank a,
WRITE
Bank a,
Col n
D
Col n
D
T0
IN
IN
NOP
NOP
D
D
T1
IN
IN
t
WR
64
PRECHARGE
(a or all)
Bank
NOP
T2
t
WR
Micron Technology, Inc. reserves the right to change products or specifications without notice.
PRECHARGE
(a or all)
Bank
T3
NOP
t RP
NOP
NOP
T4
256Mb: x4, x8, x16 SDRAM
t RP
ACTIVE
Bank a,
NOP
Row
T5
© 1999 Micron Technology, Inc. All rights reserved.
WRITE Operation
Bank a,
Don’t Care
ACTIVE
NOP
Row
T6