MT48LC4M32LFF5-8 IT:G Micron Technology Inc, MT48LC4M32LFF5-8 IT:G Datasheet
MT48LC4M32LFF5-8 IT:G
Specifications of MT48LC4M32LFF5-8 IT:G
Related parts for MT48LC4M32LFF5-8 IT:G
MT48LC4M32LFF5-8 IT:G Summary of contents
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... Refresh count – 20ns 20ns Row addressing – 20ns 20ns Bank addressing Column addressing Micron Technology, Inc., reserves the right to change products or specifications without notice. 1 128Mb: x16, x32 Mobile SDRAM Features Pb-free 2 2 Pb-free Configurations 8 Meg Meg Meg ...
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... Electrical Specifications .49 Temperature and Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 Timing Diagrams .59 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32MobileTOC.fm - Rev. M 12/08 EN 128Mb: x16, x32 Mobile SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 2 ©2001 Micron Technology, Inc. All rights reserved. Table of Contents ...
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... List of Figures Figure 2: Functional Block Diagram 8 Meg x 16 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Figure 3: Functional Block Diagram 4 Meg x 32 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Figure 4: 90-Ball FBGA Pin Assignments (Top View .10 Figure 5: 54-Pin TSOP Pin Assignments (Top View .11 Figure 6: 54-Ball VFBGA Pin Assignments (Top View .11 Figure 7: Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Figure 8: CAS Latency ...
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... FBGA, “F5/B5” Package (x32 Device), 8mm x 13mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 Figure 59: 54-Pin Plastic TSOP (400 mil .80 PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32MobileLOF.fm - Rev. M 12/08 EN 128Mb: x16, x32 Mobile SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 4 ©2001 Micron Technology, Inc. All rights reserved. List of Figures ...
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... Self Refresh Current Options (x32 .56 DD Table 23: Capacitance (FBGA Pacakge .56 Table 24: Capacitance (TSOP Pacakge .56 PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32MobileLOT.fm - Rev. M 12/08 EN 128Mb: x16, x32 Mobile SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 5 ©2001 Micron Technology, Inc. All rights reserved. List of Tables ...
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... A0–A11 select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. The SDRAM provides for programmable read or write burst lengths (BL locations, or the full page, with a burst terminate option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence ...
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... The 128Mb SDRAM device is designed to operate in 3.3V or 2.5V low-power memory systems. The 2.5V version is compatible with 1.8V I/O interface. An auto refresh mode is provided along with a power-saving, power-down mode. All inputs and outputs are LVTTL-compatible ...
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... Figure 2: Functional Block Diagram 8 Meg x 16 SDRAM CKE CLK CONTROL CS# LOGIC WE# CAS# RAS# REFRESH MODE REGISTER COUNTER 12 12 A0-A11, ADDRESS 14 BA0, BA1 REGISTER PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32Mobile_2.fm - Rev BANK0 ROW- 12 ROW- ADDRESS ADDRESS MUX 4096 LATCH & (4,096 x 512 x 16) ...
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... Figure 3: Functional Block Diagram 4 Meg x 32 SDRAM CKE CLK CONTROL CS# LOGIC WE# CAS# RAS# REFRESH MODE REGISTER COUNTER 12 12 A0–A11, ADDRESS 14 BA0, BA1 REGISTER PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN BANK0 12 BANK0 ROW- 12 ROW- ADDRESS ADDRESS MUX 4,096 LATCH & (4,096 x 256 x 32) ...
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... A5 A6 A10 CLK CKE A9 BA0 NC NC CAS# Q DQ8 DQ10 DQ9 DQ6 SS Q DQ12 DQ14 DQ1 DQ15 128Mb: x16, x32 Mobile SDRAM Pin/Ball Assignments and Descriptions 8 9 DQ23 DQ21 V Q DQ19 SS DQ20 DQ18 DQ16 DQM2 BA1 A11 CS# RAS# WE# DQM0 DQ7 DQ5 DQ3 ...
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... UDQM CLK CKE CAS# NC/A12 A11 A9 BA0 Top View (Ball Down) 11 128Mb: x16, x32 Mobile SDRAM 8 9 DQ0 V DD DQ2 DQ1 DQ4 DQ3 DQ6 DQ5 LDQM DQ7 RAS# WE# BA1 CS# A1 A10 Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... Pin/Ball Assignments and Descriptions Type Description Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. Input Clock enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. ...
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... Pin/Ball Assignments and Descriptions Type Description Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. Input Clock enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. ...
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... Pin/Ball Assignments and Descriptions Type Description Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. Input Clock enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. ...
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... Functional Description In general, the 128Mb SDRAMs (2 Meg banks and 1 Meg banks) are quad- bank DRAMs that operate at 3.3V or 2.5V and include a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x16’s 33,554,432-bit banks is organized as 4,096 rows by 512 columns by 16 bits. Each of the x32’ ...
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... Issue an AUTO REFRESH command. 11. Wait at least are allowed. 12. The SDRAM is now ready for mode register programming. Because the mode register will power unknown state, it should be loaded with desired bit values prior to applying any operational command. Using the LMR command, program the mode register ...
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... Burst Length (BL) Read and write accesses to the SDRAM are burst oriented, with BL being programmable, as shown in Figure 8 on page 20. BL determines the maximum number of column loca- tions that can be accessed for a given READ or WRITE command. Burst lengths locations are available for both the sequential and the interleaved burst types, and a full-page burst is available for the sequential mode ...
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... Valid – – – All other states reserved CAS Latency Reserved Reserved Reserved Reserved Reserved Micron Technology, Inc., reserves the right to change products or specifications without notice. 18 128Mb: x16, x32 Mobile SDRAM Register Definition Address Bus Mode Register (Mx) Burst Length Burst Length ...
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... A0–A8 for x16, A0– A7 for x32 (location 0–y) Micron Technology, Inc., reserves the right to change products or specifications without notice. 19 128Mb: x16, x32 Mobile SDRAM Register Definition Order of Accesses Within a Burst Type = Sequential Type = Interleaved 0-1 1-0 0-1-2-3 0-1-2-3 1-2-3-0 1-0-3-2 2-3-0-1 ...
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... NOP Allowable Operating Frequency (MHz) Speed -75M – ≤ ≤ 40 -10 Micron Technology, Inc., reserves the right to change products or specifications without notice. 20 128Mb: x16, x32 Mobile SDRAM Register Definition NOP OUT DON’T CARE UNDEFINED ≤ 100 ≤ 133 ≤ 100 ≤ ...
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... Operating Mode Valid Normal Operation – – All other states reserved 21 128Mb: x16, x32 Mobile SDRAM Register Definition Extended Mode Register (Ex) PASR Partial-Array Self Refresh Coverage E2 FullArray (All Banks) 0 Half Array (BA1 = 0) 0 Quarter Array (BA1 = BA0 = 0) ...
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... Every cell in the DRAM requires refreshing due to the capacitor losing its charge over time. The refresh rate is dependent on temperature. At higher temperatures a capacitor loses charge quicker than at lower temperatures, requiring the cells to be refreshed more often. Historically, during self refresh, the refresh rate has been set to accommodate the worst case, or highest temperature range, expected ...
Page 23
... DQ31. COMMAND INHIBIT The COMMAND INHIBIT function prevents new commands from being executed by the SDRAM, regardless of whether the CLK signal is enabled. The SDRAM is effectively dese- lected. Operations already in progress are not affected. NO OPERATION (NOP) The NO OPERATION (NOP) command is used to instruct the selected SDRAM to perform a NOP (RAS#, CAS#, and WE# are HIGH, and CS# is LOW) ...
Page 24
... A10 to enable auto precharge in conjunction with a specific READ or WRITE command. A precharge of the bank/row that is addressed with the READ or WRITE command is PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN 128Mb: x16, x32 Mobile SDRAM t MRD is met. t RP) after the PRECHARGE command is issued. Input A10 determines Micron Technology, Inc ...
Page 25
... SELF REFRESH The SELF REFRESH command can be used to retain data in the SDRAM, even if the rest of the system is powered down. When in the self refresh mode, the SDRAM retains data without external clocking. The SELF REFRESH command is initiated like an AUTO REFRESH command except CKE is disabled (LOW). After the SELF REFRESH command is registered, all the inputs to the SDRAM become “ ...
Page 26
... Self refresh is not supported on automotive temperature (AT) devices. Operation BANK/ROW ACTIVATION Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row in that bank must be “opened.” This is accomplished via the ACTIVE command, which selects both the bank and the row to be activated (see Figure 10). ...
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... COLUMN ADDRESS ENABLE AUTO PRECHARGE A10 DISABLE AUTO PRECHARGE BANK ADDRESS DON’T CARE 27 128Mb: x16, x32 Mobile SDRAM t CK< READ or WRITE DON’T CARE Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001 Micron Technology, Inc. All rights reserved. ...
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... COMMAND This is shown in Figure 14 on page 29 for and data element either the last of a burst of four or the last desired of a longer burst. The 128Mb SDRAM uses a pipelined architecture and, therefore, does not require the 2n rule associated with a prefetch architecture. A READ command can be initiated on any clock cycle following a previous READ command ...
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... D OUT OUT READ NOP NOP NOP BANK, COL OUT READ NOP NOP NOP BANK, COL 128Mb: x16, x32 Mobile SDRAM T4 T5 READ NOP cycles BANK, COL OUT OUT OUT READ NOP NOP cycle BANK, COL OUT OUT OUT OUT READ NOP ...
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... READ burst, provided that I/O contention can be avoided given system design, there may be a possibility that the device driving the input data will go Low-Z before the SDRAM DQ go High-Z. In this case, at least a single-cycle delay should occur between the last read data and the WRITE command. ...
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... T3 READ NOP NOP NOP BANK, COL OUT TRANSITIONING DATA READ NOP NOP NOP BANK, COL TRANSITIONING DATA 31 128Mb: x16, x32 Mobile SDRAM T4 WRITE BANK, COL DON’T CARE T4 T5 NOP WRITE BANK, COL OUT DON’T CARE Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... PRECHARGE command is that it can be used to truncate fixed-length or full-page bursts. PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN 128Mb: x16, x32 Mobile SDRAM met. Note that part of the row precharge time is Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... NOP NOP NOP BANK a, COL n D OUT CLK READ NOP NOP NOP BANK a, COL RAS(MIN) has been satisfied prior to the PRECHARGE command. 33 128Mb: x16, x32 Mobile SDRAM PRECHARGE NOP NOP ACTIVE cycles BANK BANK all) ROW D OUT OUT PRECHARGE NOP NOP ...
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... OUT OUT READ NOP NOP NOP BANK, COL n D OUT CLK READ NOP NOP NOP BANK, COL 128Mb: x16, x32 Mobile SDRAM BURST NOP NOP TERMINATE cycles D OUT OUT BURST NOP NOP TERMINATE cycle OUT OUT OUT BURST NOP NOP NOP ...
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... WRITE command, and the data provided coincident with the new command applies to the new command. An example is shown in Figure 21 on page 36. Data either the last of a burst of two or the last desired of a longer burst. The 128Mb SDRAM uses a pipe- lined architecture and, therefore, does not require the 2n rule associated with a prefetch architecture ...
Page 36
... least one clock plus time, regardless of frequency met. The PRECHARGE can be issued coincident with the second clock (see 36 128Mb: x16, x32 Mobile SDRAM t WR after the clock edge at Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001 Micron Technology, Inc. All rights reserved. ...
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... READ NOP BANK, BANK, COL n COL TRANSITIONING DATA 37 128Mb: x16, x32 Mobile SDRAM T4 T5 NOP NOP D D OUT OUT DON’T CARE Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001 Micron Technology, Inc. All rights reserved. READs ...
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... T1 T2 BURST NEXT WRITE TERMINATE COMMAND BANK, (ADDRESS) COL (DATA) n DON’T CARE 38 128Mb: x16, x32 Mobile SDRAM NOP NOP ACTIVE BANK a, ROW t RP NOP NOP ACTIVE BANK a, ROW DON’T CARE Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... RP) after the precharge command is issued REF or REF t Micron Technology, Inc., reserves the right to change products or specifications without notice. 39 128Mb: x16, x32 Mobile SDRAM ) since no refresh operations are AT CKS). See Figure 28 on page 40. ©2001 Micron Technology, Inc. All rights reserved. READs ...
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... Input buffers gated off Enter power-down mode. Exit power-down mode NOP WRITE BANK, COL TRANSITIONING DATA 40 128Mb: x16, x32 Mobile SDRAM > t CKS NOP ACTIVE t RCD t RAS t RC DON’T CARE T4 T5 NOP NOP DON’T CARE Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
Page 41
... CONCURRENT Auto Precharge An access command (READ or WRITE) to another bank while an access command with auto precharge enabled is executing is not allowed by SDRAMs, unless the SDRAM supports concurrent auto precharge. Micron SDRAMs support concurrent auto precharge. Four cases where concurrent auto precharge occurs are defined below. ...
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... NOP NOP NOP BANK n Page READ with Burst of 4 Active Page Active BANK n, COL a D OUT a CAS Latency = 3 (BANK n) TRANSITIONING DATA from contending with D OUT t 42 128Mb: x16, x32 Mobile SDRAM NOP NOP NOP NOP Idle BANK BANK n Precharge OUT OUT ...
Page 43
... BANK n Page Active WRITE with Burst of 4 Page Active BANK n, BANK m, COL a COL TRANSITIONING DATA Micron Technology, Inc., reserves the right to change products or specifications without notice. 43 128Mb: x16, x32 Mobile SDRAM NOP NOP NOP NOP Precharge BANK BANK OUT OUT (BANK m) DON’ ...
Page 44
... H Notes: 1. CKE clock edge. 2. Current state is the state of the SDRAM immediately prior to clock edge n. 3. COMMAND MAND 4. All states and sequences not shown are illegal or reserved. 5. Exiting power-down at clock edge n will put the device in the all banks idle state in time for clock edge (provided that 6 ...
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... Starts with registration of a WRITE command with auto precharge enabled and ends when will be in the idle state. Micron Technology, Inc., reserves the right to change products or specifications without notice. 45 128Mb: x16, x32 Mobile SDRAM is HIGH (see Table 9 on page 44) and has been met. ...
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... Does not affect the state of the bank and acts as a NOP to that bank. PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32Mobile_2.fm - Rev RFC is met, the SDRAM will be in the all banks idle state. Accessing mode Starts with registration of a LOAD MODE REGISTER command and t ...
Page 47
... Write w/auto Starts with registration of a WRITE command with auto precharge enabled and ends when will be in the idle state. 47 128Mb: x16, x32 Mobile SDRAM is HIGH (see Table 9 on page 44) and has been met. t RCD has been met. No ...
Page 48
... The last valid WRITE to bank n will be data registered 1 clock to the WRITE to bank m (see Figure 34 on page 43). PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN 128Mb: x16, x32 Mobile SDRAM met, where WR begins when the WRITE to bank m is reg- Micron Technology, Inc ...
Page 49
... Table 14 on page 50. To ensure the compatibility of current and future designs, contact Micron Applications Engineering to confirm thermal impedance values. The SDRAM device’s safe junction temperature range can be maintained when the T specification is not exceeded. In applications where the device’s ambient temperature is too high, use of forced air and/or heat sinks may be required to satisfy the case tempera- ture specifications ...
Page 50
... Thermal resistance data is sampled from multiple lots, and the values should be viewed as typical. 3. These are estimates; actual results may vary. 4. Thermal impedance values were obtained using the 128Mb SDRAM 54-pin TSOP. PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN 128Mb: x16, x32 Mobile SDRAM ...
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... PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN 22.22mm 11.11mm 8.00mm 4.00mm 8.00mm 4.00mm 8.00mm 4.00mm 13.00mm 6.50mm Micron Technology, Inc., reserves the right to change products or specifications without notice. 51 128Mb: x16, x32 Mobile SDRAM Electrical Specifications 10.16mm 5.08mm ©2001 Micron Technology, Inc. All rights reserved. ...
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... Data output low voltage: Logic 0; All inputs Input leakage current: Any input 0V ≤ V ≤ V (All other pins not under test = 0V Output leakage current: DQ are disabled; 0V ≤ V PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN 128Mb: x16, x32 Mobile SDRAM = +3.3V ±0.3V Symbol Min ...
Page 53
... T 0.3 1 (a) 1 CLK – +7.5ns t WR (m) 15 – t XSR 67 – Micron Technology, Inc., reserves the right to change products or specifications without notice. 53 128Mb: x16, x32 Mobile SDRAM Electrical Specifications -8 -10 Min Max Min Max Units – 7 – 7 – 8 – 8 – 19 – ...
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... Last data-in to burst STOP command Last data-in to new READ/WRITE command Last data-in to PRECHARGE command LOAD MODE REGISTER command to ACTIVE or REFRESH command Data-out to High-Z from PRECHARGE command PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN 128Mb: x16, x32 Mobile SDRAM Symbol -75M -8 t CCD 1 1 ...
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... RFC (MIN) I DD5 t RFC = 15.625µs I DD6 t RFC = 3.906µs(AT) I DD6 +1.8V ±0.15V DD Micron Technology, Inc., reserves the right to change products or specifications without notice. 55 128Mb: x16, x32 Mobile SDRAM Electrical Specifications = +3.3V ±0. Max -75M -8 -10 Units 130 130 100 mA 450 ...
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... DD6 t RFC = 3.906µs(AT) I DD6 +1.8V ±0.15V DD Symbol Symbol Micron Technology, Inc., reserves the right to change products or specifications without notice. 56 128Mb: x16, x32 Mobile SDRAM Electrical Specifications = +3.3V ±0. Max -75M -8 -10 Units 150 150 120 mA 450 450 450 µ 130 ...
Page 57
... CKS; clock(s) specified as a reference only at minimum t WR plus t WR. current will increase or decrease proportionally according to the amount 125MHz for -8 and CK = 100MHz for -10. 57 128Mb: x16, x32 Mobile SDRAM Q = +3.3V 25°C; pin under test biased at A ≤ +70°C (commercial), – A ≤ +105°C (automotive)). A and V DD ...
Page 58
... for a pulse width ≤ 3ns, and the pulse width overshoot: V (MAX WR, and PRECHARGE commands). CKE may 7.5ns; for - and 58 128Mb: x16, x32 Mobile SDRAM undershoot RP) begins at 5.4ns for - 8ns; for -10 and t RFC (MIN) else CKE is LOW. The I Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
Page 59
... RP MRD MRD Load Extended Load Mode Mode Register Register Micron Technology, Inc., reserves the right to change products or specifications without notice. 59 128Mb: x16, x32 Mobile SDRAM Timing Diagrams T7 T9 T19 ( ( ( ( ( ( ) ) ) ) ) ) ( ( ( ( ( ...
Page 60
... Two clock cycles Input buffers gated off while in power-down mode All banks idle, enter power-down mode Exit power-down mode 60 128Mb: x16, x32 Mobile SDRAM Timing Diagrams CKS NOP ACTIVE ROW ROW BANK All banks idle DON’T CARE Micron Technology, Inc., reserves the right to change products or specifications without notice. © ...
Page 61
... Rev NOP NOP NOP OUT OUT t LZ Micron Technology, Inc., reserves the right to change products or specifications without notice. 61 128Mb: x16, x32 Mobile SDRAM Timing Diagrams NOP WRITE COLUMN e 2 BANK UNDEFINED ©2001 Micron Technology, Inc. All rights reserved. T9 NOP ...
Page 62
... RP t RFC 1, 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. 62 128Mb: x16, x32 Mobile SDRAM Timing Diagrams AUTO NOP NOP ACTIVE ( ( REFRESH ) ) ( ( ) ) ( ...
Page 63
... XSR requires a minimum of 2 clocks regardless of frequency or timing general rule, any time self refresh is exited, the DRAM may not reenter the self refresh mode until all rows have been refreshed via the AUTO REFRESH command at the distrib- uted refresh rate, ( allowed ...
Page 64
... READ NOP NOP t CMS t CMH 2 COLUMN m BANK OUT t LZ CAS Latency Micron Technology, Inc., reserves the right to change products or specifications without notice. 64 128Mb: x16, x32 Mobile SDRAM Timing Diagrams NOP NOP PRECHARGE ALL BANKS SINGLE BANKS BANK( m+1 D m+2 D m+3 OUT ...
Page 65
... PDF: 09005aef807f4885/Source: 09005aef8071a76b 128Mbx16x32Mobile_2.fm - Rev READ NOP NOP t CMS t CMH COLUMN m 2 BANK OUT t LZ CAS Latency Micron Technology, Inc., reserves the right to change products or specifications without notice. 65 128Mb: x16, x32 Mobile SDRAM Timing Diagrams NOP NOP NOP OUT OUT OUT © ...
Page 66
... NOP t CMS t CMH 2 COLUMN m BANK OUT CAS Latency t Micron Technology, Inc., reserves the right to change products or specifications without notice. 66 128Mb: x16, x32 Mobile SDRAM Timing Diagrams PRECHARGE ACTIVE NOP ROW ALL BANKS ROW SINGLE BANKS BANK BANK( UNDEFINED RAS would be violated. ...
Page 67
... NOP 3 NOP 3 READ t CMS t CMH COLUMN m 2 ENABLE AUTO PRECHARGE BANK CAS Latency t RAS would be violated. Micron Technology, Inc., reserves the right to change products or specifications without notice. 67 128Mb: x16, x32 Mobile SDRAM Timing Diagrams NOP ACTIVE NOP ROW ROW BANK t AC ...
Page 68
... COLUMN m 2 ROW ROW BANK 0 BANK OUT t LZ CAS Latency - BANK 0 t RCD - BANK 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. 68 128Mb: x16, x32 Mobile SDRAM Timing Diagrams NOP READ NOP COLUMN b 2 ENABLE AUTO PRECHARGE BANK ...
Page 69
... Rev READ NOP NOP NOP t CMH BANK m+1 OUT OUT t LZ 512 (x16) locations within same row CAS Latency Full-page burst does not self-terminate. Can use BURST TERMINATE command. t RP. 69 128Mb: x16, x32 Mobile SDRAM Timing Diagrams NOP NOP BURST TERM ( ( ...
Page 70
... Rev READ NOP NOP t CMS t CMH COLUMN m 2 BANK OUT CAS Latency Micron Technology, Inc., reserves the right to change products or specifications without notice. 70 128Mb: x16, x32 Mobile SDRAM Timing Diagrams NOP NOP NOP NOP OUT OUT UNDEFINED ©2001 Micron Technology, Inc. All rights reserved. ...
Page 71
... 3> and the PRECHARGE command regardless of fre- IN Micron Technology, Inc., reserves the right to change products or specifications without notice. 71 128Mb: x16, x32 Mobile SDRAM Timing Diagrams NOP PRECHARGE NOP ALL BANKS SINGLE BANK BANK UNDEFINED ©2001 Micron Technology, Inc. All rights reserved. ...
Page 72
... WRITE NOP NOP NOP t CMH BANK Micron Technology, Inc., reserves the right to change products or specifications without notice. 72 128Mb: x16, x32 Mobile SDRAM Timing Diagrams NOP NOP NOP ©2001 Micron Technology, Inc. All rights reserved. T9 ACTIVE ROW ROW BANK DON’T CARE ...
Page 73
... COLUMN m 3 BANK m> and the PRECHARGE command regardless of frequency Micron Technology, Inc., reserves the right to change products or specifications without notice. 73 128Mb: x16, x32 Mobile SDRAM Timing Diagrams PRECHARGE NOP ACTIVE ALL BANKS ROW SINGLE BANK BANK BANK t RP RAS would be violated. ...
Page 74
... ENABLE AUTO PRECHARGE BANK m> and the PRECHARGE command, regardless of frequency RAS would be violated. Micron Technology, Inc., reserves the right to change products or specifications without notice. 74 128Mb: x16, x32 Mobile SDRAM Timing Diagrams NOP NOP NOP ACTIVE ROW ROW BANK t RP ©2001 Micron Technology, Inc. All rights reserved. ...
Page 75
... WRITE NOP ACTIVE t CMH COLUMN m 2 ROW ROW BANK 0 BANK RCD - BANK 1 75 128Mb: x16, x32 Mobile SDRAM Timing Diagrams NOP WRITE NOP NOP COLUMN b 2 ENABLE AUTO PRECHARGE BANK BANK BANK 0 Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
Page 76
... CH WRITE NOP NOP t CMH t CMS COLUMN m 1 BANK 512 (x16) locations within same row Full page completed t RP. Micron Technology, Inc., reserves the right to change products or specifications without notice. 76 128Mb: x16, x32 Mobile SDRAM Timing Diagrams NOP NOP BURST TERM ( ...
Page 77
... NOP WRITE NOP t CMS t CMH COLUMN m 2 ENABLE AUTO PRECHARGE DISABLE AUTO PRECHARGE BANK 128Mb: x16, x32 Mobile SDRAM Timing Diagrams NOP NOP NOP NOP DON’T CARE Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001 Micron Technology, Inc. All rights reserved. ...
Page 78
... C L 8.00 ±0.10 0.80 TYP C L 4.00 ±0.05 Micron Technology, Inc., reserves the right to change products or specifications without notice. 78 128Mb: x16, x32 Mobile SDRAM Package Dimensions SOLDER BALL MATERIAL: 62% Sn, 36% Pb 96.5% Sn, 3% Ag, 0.5% Cu SOLDER MASK DEFINED BALL PADS: Ø0.40 SUBSTRATE MATERIAL: PLASTIC LAMINATE ...
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... TYP BALL A1 ID BALL 13.00 ±0.10 6.50 ±0. 4.00 ±0.05 8.00 ±0.10 79 128Mb: x16, x32 Mobile SDRAM Package Dimensions SOLDER BALL MATERIAL: 62% Sn, 36% Pb 96.5% Sn, 3%Ag, 0.5% Cu SUBSTRATE MATERIAL: PLASTIC LAMINATE MOLD COMPOUND: EPOXY NOVOLAC BALL A1 ID 1.00 MAX www ...
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... MAX 0.10 ® their respective owners. characterization sometimes occur. Micron Technology, Inc., reserves the right to change products or specifications without notice. 80 128Mb: x16, x32 Mobile SDRAM Package Dimensions SEE DETAIL A GAGE PLANE +0.10 -0.05 0.50 ±0.10 DETAIL A ©2001 Micron Technology, Inc. All rights reserved. ...