XC3S500E-5PQG208C Xilinx Inc, XC3S500E-5PQG208C Datasheet - Page 139

• Manufacturer Part Number: XC3S500E-5PQG208C
• Description: FPGA Spartan®-3E Family 500K Gates 10476 Cells 657MHz 90nm (CMOS) Technology 1.2V 208-Pin PQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-3Er

Specifications of XC3S500E-5PQG208C

• Package: 208PQFP
• Family Name: Spartan®-3E
• Device Logic Cells: 10476
• Device Logic Units: 1164
• Device System Gates: 500000
• Number Of Registers: 9312
• Maximum Internal Frequency: 657 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 158
• Ram Bits: 368640
• Package / Case: 208-MQFP, 208-PQFP
• Mounting Type: Surface Mount
• Voltage - Supply: 1.1 V ~ 3.465 V
• Operating Temperature: 0°C ~ 85°C
• Number Of I /o: 158
• Number Of Logic Elements/cells: *
• Number Of Gates: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 99: CLB Distributed RAM Switching Characteristics
Table 100: CLB Shift Register Switching Characteristics
DS312-3 (v3.8) August 26, 2009
Product Specification
Clock-to-Output Times
Setup Times
Hold Times
Clock Pulse Width
Clock-to-Output Times
Setup Times
Hold Times
Clock Pulse Width
T
T
WPH
WPH
T
Symbol
Symbol
T
T
T
AH,
T
SHCKO
SRLDS
SRLDH
T
T
T
T
REG
WS
AS
DH
DS
, T
, T
T
WH
WPL
WPL
R
Time from the active edge at the CLK input to data
appearing on the distributed RAM output
Setup time of data at the BX or BY input before the active
transition at the CLK input of the distributed RAM
Setup time of the F/G address inputs before the active
transition at the CLK input of the distributed RAM
Setup time of the write enable input before the active
transition at the CLK input of the distributed RAM
Hold time of the BX, BY data inputs after the active
transition at the CLK input of the distributed RAM
Hold time of the F/G address inputs or the write enable
input after the active transition at the CLK input of the
distributed RAM
Minimum High or Low pulse width at CLK input
Time from the active edge at the CLK input to data
appearing on the shift register output
Setup time of data at the BX or BY input before the active
transition at the CLK input of the shift register
Hold time of the BX or BY data input after the active
transition at the CLK input of the shift register
Minimum High or Low pulse width at CLK input
Description
Description
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0.40
0.46
0.34
0.13
0.88
0.41
0.14
0.88
Min
Min
0
-
-
-5
-5
DC and Switching Characteristics
Max
2.05
Max
3.62
-
-
-
-
-
-
-
-
-
0.46
0.52
0.40
0.15
1.01
0.46
0.16
1.01
Min
Min
0
-
-
-4
-4
Max
2.35
Max
4.16
-
-
-
-
-
-
-
-
-
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
139