XC3S500E-5PQG208C Xilinx Inc, XC3S500E-5PQG208C Datasheet - Page 157

• Manufacturer Part Number: XC3S500E-5PQG208C
• Description: FPGA Spartan®-3E Family 500K Gates 10476 Cells 657MHz 90nm (CMOS) Technology 1.2V 208-Pin PQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-3Er

Specifications of XC3S500E-5PQG208C

• Package: 208PQFP
• Family Name: Spartan®-3E
• Device Logic Cells: 10476
• Device Logic Units: 1164
• Device System Gates: 500000
• Number Of Registers: 9312
• Maximum Internal Frequency: 657 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 158
• Ram Bits: 368640
• Package / Case: 208-MQFP, 208-PQFP
• Mounting Type: Surface Mount
• Voltage - Supply: 1.1 V ~ 3.465 V
• Operating Temperature: 0°C ~ 85°C
• Number Of I /o: 158
• Number Of Logic Elements/cells: *
• Number Of Gates: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 119: Configuration Timing Requirements for Attached SPI Serial Flash
DS312-3 (v3.8) August 26, 2009
Product Specification
Notes:
1.
2.
T
T
T
T
f
C
Symbol
CCS
DSU
DH
V
or f
These requirements are for successful FPGA configuration in SPI mode, where the FPGA provides the CCLK frequency. The post
configuration timing can be different to support the specific needs of the application loaded into the FPGA and the resulting clock source.
Subtract additional printed circuit board routing delay as required by the application.
R
R
SPI serial Flash PROM chip-select time
SPI serial Flash PROM data input setup time
SPI serial Flash PROM data input hold time
SPI serial Flash PROM data clock-to-output time
Maximum SPI serial Flash PROM clock frequency (also depends
on specific read command used)
Description
www.xilinx.com
T
T
T
CCS
V
f
DSU
DC and Switching Characteristics
C
T
≤
≥
DH
T
Requirement
≤
≤
------------------------------ -
T
MCCLn
T
≤
T
CCLKn min
MCCL1
MCCL1
T
MCCH1
1
–
(
T
–
–
DCC
T
)
T
CCO
CCO
Units
MHz
ns
ns
ns
ns
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