XC3S700AN-4FG484I Xilinx Inc, XC3S700AN-4FG484I Datasheet - Page 51

• Manufacturer Part Number: XC3S700AN-4FG484I
• Description: FPGA Spartan®-3AN Family 700K Gates 13248 Cells 667MHz 90nm Technology 1.2V 484-Pin FBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3ANr

Specifications of XC3S700AN-4FG484I

• Package: 484FBGA
• Family Name: Spartan®-3AN
• Device Logic Units: 13248
• Device System Gates: 700000
• Maximum Internal Frequency: 667 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 372
• Ram Bits: 368640
• Number Of Logic Elements/cells: 13248
• Number Of Labs/clbs: 1472
• Total Ram Bits: 368640
• Number Of I /o: 372
• Number Of Gates: 700000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-BBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Block RAM Timing
Table 38: Block RAM Timing
DS557 (v4.1) April 1, 2011
Product Specification
Notes:
1.
Clock-to-Output Times
T
Setup Times
T
T
T
T
Hold Times
T
T
T
T
Clock Timing
T
T
Clock Frequency
F
RCKO
RCCK_ADDR
RDCK_DIB
RCCK_ENB
RCCK_WEB
RCKC_ADDR
RCKD_DIB
RCKC_ENB
RCKC_WEB
BPWH
BPWL
BRAM
Symbol
The numbers in this table are based on the operating conditions set forth in
When reading from block RAM, the delay from the active
transition at the CLK input to data appearing at the DOUT
output
Setup time for the ADDR inputs before the active transition at
the CLK input of the block RAM
Setup time for data at the DIN inputs before the active
transition at the CLK input of the block RAM
Setup time for the EN input before the active transition at the
CLK input of the block RAM
Setup time for the WE input before the active transition at the
CLK input of the block RAM
Hold time on the ADDR inputs after the active transition at the
CLK input
Hold time on the DIN inputs after the active transition at the
CLK input
Hold time on the EN input after the active transition at the CLK
input
Hold time on the WE input after the active transition at the CLK
input
High pulse width of the CLK signal
Low pulse width of the CLK signal
Block RAM clock frequency
Description
www.xilinx.com
Spartan-3AN FPGA Family: DC and Switching Characteristics
Table
0.32
0.28
0.69
1.12
1.56
1.56
Min
10.
–
0
0
0
0
0
-5
Max
2.06
320
Speed Grade
–
–
–
–
–
–
–
–
–
–
0.36
0.31
0.77
1.26
1.79
1.79
Min
–
0
0
0
0
0
-4
Max
2.49
280
–
–
–
–
–
–
–
–
–
–
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
51