XC3S700AN-4FG484I Xilinx Inc, XC3S700AN-4FG484I Datasheet - Page 60

• Manufacturer Part Number: XC3S700AN-4FG484I
• Description: FPGA Spartan®-3AN Family 700K Gates 13248 Cells 667MHz 90nm Technology 1.2V 484-Pin FBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3ANr

Specifications of XC3S700AN-4FG484I

• Package: 484FBGA
• Family Name: Spartan®-3AN
• Device Logic Units: 13248
• Device System Gates: 700000
• Maximum Internal Frequency: 667 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 372
• Ram Bits: 368640
• Number Of Logic Elements/cells: 13248
• Number Of Labs/clbs: 1472
• Total Ram Bits: 368640
• Number Of I /o: 372
• Number Of Gates: 700000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-BBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Configuration and JTAG Timing
General Configuration Power-On/Reconfigure Timing
X-Ref Target - Figure 13
Table 50: Power-On Timing and the Beginning of Configuration
DS557 (v4.1) April 1, 2011
Product Specification
Notes:
1.
2.
3.
4.
T
T
T
T
T
POR
PROG
PL
INIT
ICCK
(2)
The numbers in this table are based on the operating conditions set forth in
and V
Power-on reset and the clearing of configuration memory occurs during this period.
This specification applies only to the Master Serial, SPI, and BPI modes.
For details on configuration, see
(2)
Symbol
(3)
Notes:
1.
2.
3.
V
CCAUX
(Open-Drain)
CCO
PROG_B
When configuring from the In-System Flash, V
sure V
V
The Low-going pulse on PROG_B is optional after power-on but necessary for reconfiguration without a power cycle.
The rising edge of INIT_B samples the voltage levels applied to the mode pins (M0 - M2).
(Supply)
V
(Supply)
(Supply)
CCO
V
(Output)
Bank 2
CCAUX
lines.
(Input)
INIT_B
CCINT
CCLK
supplies to the FPGA can be applied in any order if this requirement is met.
CCAUX
The time from the application of V
Bank 2 supply voltage ramps (whichever occurs last) to the
rising transition of the INIT_B pin
The width of the low-going pulse on the PROG_B pin
The time from the rising edge of the PROG_B pin to the
rising transition on the INIT_B pin
Minimum Low pulse width on INIT_B output
The time from the rising edge of the INIT_B pin to the
generation of the configuration clock signal at the CCLK
output pin
Figure 13: Waveforms for Power-On and the Beginning of Configuration
reaches at least 3.0V before INIT_B goes High to indicate the start of configuration. V
UG332
Spartan-3 Generation Configuration User Guide.
Description
1.0V
2.0V
2.0V
CCINT
CCAUX
T
T
www.xilinx.com
POR
PROG
, V
Spartan-3AN FPGA Family: DC and Switching Characteristics
must be in the recommended operating range; on power-up make
CCAUX
, and V
T
Table
PL
CCO
10. This means power must be applied to all V
All
All
XC3S50AN
XC3S200AN
XC3S400AN
XC3S700AN
XC3S1400AN
All
All
T
Device
ICCK
All Speed Grades
Min
250
0.5
0.5
–
–
–
–
–
–
CCINT
, V
DS557-3_01_052908
CCAUX
Max
0.5
0.5
18
–
1
2
2
–
4
, and
1.2V
3.3V
3.3V
2.5V
or
CCINT
Units
, V
ms
ms
ms
ms
ms
ms
µs
ns
µs
CCO
60
,