XC5VLX220T-2FF1738I Xilinx Inc, XC5VLX220T-2FF1738I Datasheet - Page 13
![FPGA Virtex®-5 Family 221184 Cells 65nm (CMOS) Technology 1V 1738-Pin FCBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX220T-2FF1738I
Manufacturer Part Number
XC5VLX220T-2FF1738I
Description
FPGA Virtex®-5 Family 221184 Cells 65nm (CMOS) Technology 1V 1738-Pin FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX220T-2FF1738I
Package
1738FCBGA
Family Name
Virtex®-5
Device Logic Units
221184
Typical Operating Supply Voltage
1 V
Maximum Number Of User I/os
680
Ram Bits
7815168
Number Of Logic Elements/cells
221184
Number Of Labs/clbs
17280
Total Ram Bits
7815168
Number Of I /o
680
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1738-BBGA, FCBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With
HW-AFX-FF1738-500-G - BOARD DEV VIRTEX 5 FF1738
Number Of Gates
-
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VLX220T-2FF1738I
Manufacturer:
Xilinx Inc
Quantity:
10 000
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Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Block RAM Initialization in VHDL or Verilog Code
Additional RAMB18 and RAMB36 Primitive Design Considerations
Additional Block RAM Primitives
Block RAM Applications
Block RAM Timing Model
Block RAM Retargeting
Built-in FIFO Support
FIFO Architecture: a Top-Level View
FIFO Primitives
FIFO Port Descriptions
FIFO Operations
FIFO Attributes
FIFO VHDL and Verilog Templates
Output Latches Initialization - INIT (INIT_A or INIT_B) . . . . . . . . . . . . . . . . . . . . . . 129
Output Latches/Registers Synchronous Set/Reset (SRVAL_[A|B]) . . . . . . . . . . . . . 130
Optional Output Register On/Off Switch - DO[A|B]_REG . . . . . . . . . . . . . . . . . . . . 130
Extended Mode Address Determinant - RAM_EXTENSION_[A|B] . . . . . . . . . . . . 130
Read Width - READ_WIDTH_[A|B] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Write Width - WRITE_WIDTH_[A|B] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Write Mode - WRITE_MODE_[A|B] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Block RAM Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Optional Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Independent Read and Write Port Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
RAMB18 and RAMB36 Port Mapping Design Rules . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Cascadable Block RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Byte-wide Write Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Creating Larger RAM Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Block RAM SSR in Register Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Block RAM Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Block RAM Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Block RAM Timing Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Multirate FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Synchronous FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Status Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
FIFO Almost Full/Empty Flag Offset Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Clock Event 1
Clock Event 2
Clock Event 4
Clock Event 5
Synchronous FIFO Implementations
Standard Mode
First Word Fall Through (FWFT) Mode
Empty Flag
Almost Empty Flag
Read Error Flag
Full Flag
Write Error Flag
Almost Full Flag
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www.xilinx.com
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