XC5VLX220T-2FF1738I Xilinx Inc, XC5VLX220T-2FF1738I Datasheet - Page 221
![FPGA Virtex®-5 Family 221184 Cells 65nm (CMOS) Technology 1V 1738-Pin FCBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX220T-2FF1738I
Manufacturer Part Number
XC5VLX220T-2FF1738I
Description
FPGA Virtex®-5 Family 221184 Cells 65nm (CMOS) Technology 1V 1738-Pin FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX220T-2FF1738I
Package
1738FCBGA
Family Name
Virtex®-5
Device Logic Units
221184
Typical Operating Supply Voltage
1 V
Maximum Number Of User I/os
680
Ram Bits
7815168
Number Of Logic Elements/cells
221184
Number Of Labs/clbs
17280
Total Ram Bits
7815168
Number Of I /o
680
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1738-BBGA, FCBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With
HW-AFX-FF1738-500-G - BOARD DEV VIRTEX 5 FF1738
Number Of Gates
-
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VLX220T-2FF1738I
Manufacturer:
Xilinx Inc
Quantity:
10 000
- XC5VLX30-1FFG324C PDF datasheet
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Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
without connecting the VRN/VRP pins on these banks to external resistors. DCI
impedance control in cascaded banks is received from the master bank.
When using DCI cascading, the DCI control circuitry in the master bank creates and routes
DCI control to the cascaded banks in daisy-chain style. Only the master bank’s VRN/VRP
pins are required when using DCI cascading.
Also, when using DCI cascading, only one set of VRN/VRP pins provides the DCI
reference voltage for multiple banks. DCI cascading:
•
•
•
Similarly, due to the center column architecture, the half-size banks 1, 2, 3, and 4 are
separated from all the other banks in the center column by the CMT tiles. It is not possible
to cascade across the CMT tiles. This affects the larger devices that have more than four
user I/O center column banks (plus bank 0). For instance, bank 4 cannot be cascaded with
bank 6, and bank 3 cannot be cascaded with bank 5. Bank 3 can only be cascaded with bank
1, and bank 4 can only be cascaded with bank 2.
Figure 6-5
Reduces overall power, since fewer voltage references are required
Frees up VRN/VRP pins on slave banks for general customer use
DCI in banks 1 and 2 is supported only through cascading. These two banks do not
have VRN/VRP pins and therefore cannot be used as master or stand-alone DCI
banks. Cascading is not possible through bank 0.
shows DCI cascading support over multiple banks. Bank B is the master bank.
www.xilinx.com
SelectIO Resources General Guidelines
221
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