XC5VLX220T-2FF1738I Xilinx Inc, XC5VLX220T-2FF1738I Datasheet - Page 325
![FPGA Virtex®-5 Family 221184 Cells 65nm (CMOS) Technology 1V 1738-Pin FCBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX220T-2FF1738I
Manufacturer Part Number
XC5VLX220T-2FF1738I
Description
FPGA Virtex®-5 Family 221184 Cells 65nm (CMOS) Technology 1V 1738-Pin FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX220T-2FF1738I
Package
1738FCBGA
Family Name
Virtex®-5
Device Logic Units
221184
Typical Operating Supply Voltage
1 V
Maximum Number Of User I/os
680
Ram Bits
7815168
Number Of Logic Elements/cells
221184
Number Of Labs/clbs
17280
Total Ram Bits
7815168
Number Of I /o
680
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1738-BBGA, FCBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With
HW-AFX-FF1738-500-G - BOARD DEV VIRTEX 5 FF1738
Number Of Gates
-
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
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Manufacturer
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Company:
Part Number:
XC5VLX220T-2FF1738I
Manufacturer:
Xilinx Inc
Quantity:
10 000
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Input/Output Delay Element (IODELAY)
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Every I/O block contains a programmable absolute delay element called IODELAY. The
IODELAY can be connected to an ILOGIC/ISERDES or OLOGIC/OSERDES block or both.
IODELAY is a 64-tap, wraparound, delay element with a calibrated tap resolution. See the
Virtex-5 FPGA Data Sheet. It can be applied to the combinatorial input path, registered
input path, combinatorial output path, or registered output path. It can also be accessed
directly in the fabric. IODELAY allows incoming signals to be delayed on an individual
basis. The tap delay resolution is varied by selecting an IDELAYCTRL reference clock from
the range specified in the Virtex-5 FPGA Data Sheet. The IODELAY resource can function as
IDELAY, ODELAY, or bidirectional delay.
When used as IDELAY, the data input comes from either IBUF or the fabric and the output
goes to ILOGIC/ISERDES. There are three modes of operation available:
•
•
•
When used as ODELAY, the data input comes from OLOGIC/OSERDES and the data
output goes to OBUF. There is a single mode of operation:
•
When used as bidirectional delay, the IOB is configured in bidirectional mode. IODELAY
alternately delays the data on the input path and output path. There are two modes of
operation:
•
Zero-hold time delay mode (IDELAY_TYPE = DEFAULT)
This mode of operation allows backward compatibility for designs using the zero-hold
time delay feature in Virtex-II, Virtex-II Pro and Virtex-4 devices. This delay element is
used to provide non-positive hold times when global clocks are used without DCMs to
capture data (pin-to-pin parameters). When used in this mode, the IDELAYCTRL
primitive does not need to be instantiated. See
Guidelines
Fixed delay mode (IDELAY_TYPE = FIXED)
In the fixed delay mode, the delay value is preset at configuration to the tap number
determined by the attribute IDELAY_VALUE. Once configured, this value cannot be
changed. When used in this mode, the IDELAYCTRL primitive must be instantiated.
See
Variable delay mode (IDELAY_TYPE = VARIABLE)
In the variable delay mode, the delay value can be changed after configuration by
manipulating the control signals CE and INC. When used in this mode, the
IDELAYCTRL primitive must be instantiated. See
Guidelines
Fixed delay output mode
In the fixed delay output mode, the delay value is preset at configuration to the tap
number determined by the attribute ODELAY_VALUE. Once configured, this value
cannot be changed. When used in this mode, the IDELAYCTRL primitive must be
instantiated. See
Fixed IDELAY (IDELAY_TYPE = FIXED) and fixed ODELAY mode
In this mode, both the values for IDELAY and ODELAY are preset at configuration and
are determined by the IDELAY_VALUE and ODELAY_VALUE attributes. Once
configured, this value cannot be changed. When used in this mode, the IDELAYCTRL
primitive must be instantiated. See
more details.
IDELAYCTRL Usage and Design Guidelines
for more details.
for more details.
IDELAYCTRL Usage and Design Guidelines
www.xilinx.com
IDELAYCTRL Usage and Design Guidelines
Input/Output Delay Element (IODELAY)
IDELAYCTRL Usage and Design
for more details.
IDELAYCTRL Usage and Design
for more details.
for
325
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