XC5VLX220T-2FF1738I Xilinx Inc, XC5VLX220T-2FF1738I Datasheet - Page 376
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XC5VLX220T-2FF1738I
Manufacturer Part Number
XC5VLX220T-2FF1738I
Description
FPGA Virtex®-5 Family 221184 Cells 65nm (CMOS) Technology 1V 1738-Pin FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX220T-2FF1738I
Package
1738FCBGA
Family Name
Virtex®-5
Device Logic Units
221184
Typical Operating Supply Voltage
1 V
Maximum Number Of User I/os
680
Ram Bits
7815168
Number Of Logic Elements/cells
221184
Number Of Labs/clbs
17280
Total Ram Bits
7815168
Number Of I /o
680
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1738-BBGA, FCBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With
HW-AFX-FF1738-500-G - BOARD DEV VIRTEX 5 FF1738
Number Of Gates
-
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VLX220T-2FF1738I
Manufacturer:
Xilinx Inc
Quantity:
10 000
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Chapter 8: Advanced SelectIO Logic Resources
376
Guidelines for Expanding the Parallel-to-Serial Converter Bit Width
Figure 8-16
master and slave OSERDES modules. Ports Q3-Q6 are used for the last four bits of the
parallel interface on the slave OSERDES (LSB to MSB).
X-Ref Target - Figure 8-16
Table 8-8
Table 8-8: OSERDES SDR/DDR Data Width Availability
1.
2.
3.
4.
5.
The slave inputs used for data widths requiring width expansion are listed in
Table 8-9: Slave Inputs Used for Data Width Expansion
SDR Data Widths
DDR Data Widths
Data Inputs[0:5]
Data Inputs[6:9]
Both the OSERDES modules must be adjacent master and slave pairs.
Set the SERDES_MODE attribute for the master OSERDES to MASTER and the slave
OSERDES to SLAVE. See
The user must connect the SHIFTIN ports of the MASTER to the SHIFTOUT ports of
the SLAVE.
The SLAVE only uses the ports D3 to D6 as an input.
DATA_WIDTH for Master and Slave are equal. See
Data Width
lists the data width availability for SDR and DDR mode.
illustrates a block diagram of a 10:1 DDR parallel-to-serial converter using the
Figure 8-16: Block Diagram of OSERDES Width Expansion
10
7
8
www.xilinx.com
SERDES_MODE
2, 3, 4, 5, 6, 7, 8
4, 6, 8, 10
SERDES_MODE = MASTER
D1
D2
D3
D4
D5
D6
D1
D2
D3
D4
D5
D6
Slave Inputs Used
SERDES_MODE=SLAVE
SHIFTOUT1 SHIFTOUT2
SHIFTIN1
D3–D4
D3–D6
OSERDES
OSERDES
D3
(Master)
(Slave)
Attribute.
SHIFTIN2
DATA_WIDTH
OQ
OQ
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Attribute.
ug190_8_16_100307
Data Out
Table
8-9.
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