PN5120A0HN1/C1 NXP Semiconductors, PN5120A0HN1/C1 Datasheet - Page 16

• Manufacturer Part Number: PN5120A0HN1/C1
• Description: RF Wireless Misc COMBO ANALOG/DIGI IC
• Manufacturer: NXP Semiconductors
• Type: Transmission Moduler

Specifications of PN5120A0HN1/C1

• Package / Case: HVQFN EP
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 30 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PN5120A0HN1/C1,157

NXP Semiconductors
111334
Product data sheet
8.2.1.5 CommIRqReg
Contains Interrupt Request bits.
Table 15.
Table 16.
All bits in the register CommIRqReg shall be cleared by software.
Bit
7
6
5
4
3
2
1
0
Access
Rights
Symbol
Set1
TxIRq
RxIRq
IdleIRq
HiAlertIRq
LoAlertIRq Set to logic 1, when bit LoAlert in register Status1Reg is set. In opposition to
ErrIRq
TimerIRq
CommIRqReg register (address 04h); reset value: 14h, 00010100b
Description of CommIRqReg bits
Set1
w
7
Description
Set to logic 1, Set1 defines that the marked bits in the register CommIRqReg
are set.
Set to logic 0, Set1 defines, that the marked bits in the register CommIRqReg
are cleared.
Set to logic 1 immediately after the last bit of the transmitted data was sent out.
Set to logic 1 when the receiver detects the end of a valid datastream.
If the bit RxNoErr in register RxModeReg is set to logic 1, bit RxIRq is only set
to logic 1 when data bytes are available in the FIFO.
Set to logic 1, when a command terminates by itself e.g. when the
CommandReg changes its value from any command to the Idle Command.
If an unknown command is started, the CommandReg changes its content to
the idle state and the bit IdleIRq is set. Starting the Idle Command by the
μ-Controller does not set bit IdleIRq.
Set to logic 1, when bit HiAlert in register Status1Reg is set. In opposition to
HiAlert, HiAlertIRq stores this event and can only be reset as indicated by bit
Set1.
LoAlert, LoAlertIRq stores this event and can only be reset as indicated by bit
Set1.
Set to logic 1 if any error bit in the Error Register is set.
Set to logic 1 when the timer decrements the TimerValue Register to zero.
TxIRq
Rev. 3.4 — 8 September 2009
dy
6
RxIRq
dy
5
IdleIRq
dy
4
HiAlertIRq LoAlertIRq
dy
3
dy
2
Transmission Module
© NXP B.V. 2010. All rights reserved.
ErrIRq
dy
1
PN512
TimerIRq
16 of 131
dy
PUBLIC
0