MT48LC16M8A2TG-75:G Micron Technology Inc, MT48LC16M8A2TG-75:G Datasheet - Page 61

• Manufacturer Part Number: MT48LC16M8A2TG-75:G
• Description: DRAM Chip SDRAM 128M-Bit 16Mx8 3.3V 54-Pin TSOP-II Tray
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48LC16M8A2TG-75:G

• Package: 54TSOP-II
• Density: 128 Mb
• Address Bus Width: 14 Bit
• Operating Supply Voltage: 3.3 V
• Maximum Clock Rate: 133 MHz
• Maximum Random Access Time: 6|5.4 ns
• Operating Temperature: 0 to 70 °C

Figure 45:
PDF: 09005aef8091e66d/Source: 09005aef8091e625
128MSDRAM_2.fm - Rev. N 1/09 EN
DQML, DQMU
A0–A9, A11
COMMAND
BA0, BA1
DQM /
CKE
CLK
A10
DQ
t CKS
t CMS
t AS
t AS
t AS
Single READ – With
ACTIVE
T0
ROW
ROW
BANK
t CMH
t CKH
t AH
t AH
t AH
Notes:
t RCD
t RAS
t RC
t CK
T1
1. For this example, BL = 1, and CL = 2.
2. x16: A9 and A11 = “Don’t Care.”
3. READ command not allowed or
NOP
x8: A11 = “Don’t Care.”
t CL
Auto Precharge
T2
NOP 2
t CH
T3
NOP 2
ENABLE AUTO PRECHARGE
t CMS
61
COLUMN m 3
BANK
T4
READ
t
t CMH
CAS Latency
RAS would be violated.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T5
NOP
t AC
t RP
D
T6
128Mb: x4, x8, x16 SDRAM
OUT
NOP
t OH
m
t HZ
©1999 Micron Technology, Inc. All rights reserved.
ACTIVE
ROW
BANK
T7
ROW
Timing Diagrams
T8
NOP
DON’T CARE
UNDEFINED