AD1674AR Analog Devices Inc, AD1674AR Datasheet - Page 11

• Manufacturer Part Number: AD1674AR
• Description: ADC Single SAR 100KSPS 12-Bit Parallel 28-Pin SOIC W
• Manufacturer: Analog Devices Inc

Specifications of AD1674AR

• Package: 28SOIC W
• Resolution: 12 Bit
• Sampling Rate: 100 KSPS
• Architecture: SAR
• Number Of Adcs: 1
• Number Of Analog Inputs: 2
• Digital Interface Type: Parallel
• Input Type: Voltage
• Polarity Of Input Voltage: Unipolar|Bipolar
• Rohs Status: RoHS non-compliant
• Number Of Bits: 12
• Sampling Rate (per Second): 100k
• Data Interface: Parallel
• Number Of Converters: 1
• Power Dissipation (max): 825mW
• Voltage Supply Source: Dual ±
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (0.300", 7.50mm Width)

REV. C
The full-scale trim is done by applying a signal 1 1/2 LSB below
the nominal full scale (9.9963 V for a 10 V range) and adjusting
R2 until the last transition is located (1111 1111 1110 to 1111
1111 1111). If full-scale adjustment is not required, R2 should
be replaced with a fixed 50
OUT is connected directly to REF IN, the additional full-scale
error will be approximately 1%.
BIPOLAR RANGE INPUTS
The connections for the bipolar-input mode are shown in Figure
12. Either or both of the trimming potentiometers can be
replaced with 50
accuracy limits are sufficient for the application. If the pins are
shorted together, the additional offset and gain errors will be
approximately 1%.
To trim bipolar offset to its nominal value, apply a signal 1/2
LSB below midrange (–1.22 mV for a 5 V range) and adjust
R1 until the major carry transition is located (0111 1111 1111
to 1000 0000 0000). To trim the full-scale error, apply a signal
1 1/2 LSB below full scale (+4.9963 V for a 5 V range) and
adjust R2 to give the last positive transition (1111 1111 1110 to
1111 1111 1111). These trims are interactive so several itera-
tions may be necessary for convergence.
A single-pass calibration can be done by substituting a negative
full-scale trim for the bipolar offset trim (error at midscale),
using the same circuit. First, apply a signal 1/2 LSB above minus
full scale (–4.9988 V for a 5 V range) and adjust R1 until the
minus full-scale transition is located (0000 0000 0001 to 0000
0000 0000). Then perform the gain error trim as outlined above.
Figure 12. Bipolar Input Connections with Gain and Offset
Trims
ANALOG
Figure 11. Unipolar Input Connections with Gain and
Offset Trims
–15V
INPUTS
ANALOG
100
INPUTS
100k
0 TO +20V
0 TO +10V
100k
R1
±10V
±5V
100
R2
+15V
100
100
R2
R1
1% fixed resistors if the specified AD1674
10 REF IN
12 BIP OFF
13 10V
14 20V
2
3
4
5
8
9
6
R/C
ANA COM
10 REF IN
12 BIP OFF
13 10V
12/8
CS
A
CE
REF OUT
2
3
4
5
8
14 20V
9
6
0
1% metal film resistor. If REF
R/C
ANA COM
IN
IN
12/8
CS
A
CE
REF OUT
0
AD1674
IN
IN
AD1674
MIDDLE BITS
DIG COM 15
MIDDLE BITS
HIGH BITS
LOW BITS
DIG COM 15
STS 28
+15V
–15V 11
HIGH BITS
LOW BITS
+5V
STS 28
+15V
–15V 11
20-23
16-19
24-27
+5V
20-23
16-19
24-27
1
7
7
1
–11–
REFERENCE DECOUPLING
It is recommended that a 10 F tantalum capacitor be con-
nected between REF IN (Pin 10) and ground. This has the
effect of improving the S/(N+D) ratio through filtering possible
broad-band noise contributions from the voltage reference.
BOARD LAYOUT
Designing with high resolution data converters requires careful
attention to board layout. Trace impedance is a significant issue.
At the 12-bit level, a 5 mA current through a 0.5
develop a voltage drop of 2.5 mV, which is 1 LSB for a 10 V
full-scale range. In addition to ground drops, inductive and ca-
pacitive coupling need to be considered, especially when high
accuracy analog signals share the same board with digital sig-
nals. Finally, power supplies should be decoupled in order to
filter out ac noise.
The AD1674 has a wide bandwidth sampling front end. This
means that the AD1674 will “see” high frequency noise at the
input, which nonsampling (or limited-bandwidth sampling)
ADCs would ignore. Therefore, it’s important to make an effort
to eliminate such high frequency noise through decoupling or by
using an anti-aliasing filter at the analog input of the AD1674.
Analog and digital signals should not share a common path.
Each signal should have an appropriate analog or digital return
routed close to it. Using this approach, signal loops enclose a
small area, minimizing the inductive coupling of noise. Wide PC
tracks, large gauge wire, and ground planes are highly recom-
mended to provide low impedance signal paths. Separate analog
and digital ground planes are also desirable, with a single inter-
connection point to minimize ground loops. Analog signals
should be routed as far as possible from digital signals and
should cross them (if necessary) only at right angles.
The AD1674 incorporates several features to help the user’s lay-
out. Analog pins are adjacent to help isolate analog from digital
signals. Ground currents have been minimized by careful circuit
architecture. Current through AGND is 2.2 mA, with little
code-dependent variation. The current through DGND is domi-
nated by the return current for DB11–DB0.
SUPPLY DECOUPLING
The AD1674 power supplies should be well filtered, well regu-
lated, and free from high frequency noise. Switching power sup-
plies are not recommended due to their tendency to generate
spikes which can induce noise in the analog system.
Decoupling capacitors should be used in very close layout prox-
imity between all power supply pins and ground. A 10 F tanta-
lum capacitor in parallel with a 0.1 F disc ceramic capacitor
provides adequate decoupling over a wide range of frequencies.
An effort should be made to minimize the trace length between
the capacitor leads and the respective converter power supply
and common pins. The circuit layout should attempt to locate
the AD1674, associated analog input circuitry, and interconnec-
tions as far as possible from logic circuitry. A solid analog
ground plane around the AD1674 will isolate large switching
ground currents. For these reasons, the use of wire-wrap circuit
construction is not recommended; careful printed-circuit con-
struction is preferred.
AD1674
trace will