AD1674AR Analog Devices Inc, AD1674AR Datasheet - Page 4

• Manufacturer Part Number: AD1674AR
• Description: ADC Single SAR 100KSPS 12-Bit Parallel 28-Pin SOIC W
• Manufacturer: Analog Devices Inc

Specifications of AD1674AR

• Package: 28SOIC W
• Resolution: 12 Bit
• Sampling Rate: 100 KSPS
• Architecture: SAR
• Number Of Adcs: 1
• Number Of Analog Inputs: 2
• Digital Interface Type: Parallel
• Input Type: Voltage
• Polarity Of Input Voltage: Unipolar|Bipolar
• Rohs Status: RoHS non-compliant
• Number Of Bits: 12
• Sampling Rate (per Second): 100k
• Data Interface: Parallel
• Number Of Converters: 1
• Power Dissipation (max): 825mW
• Voltage Supply Source: Dual ±
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (0.300", 7.50mm Width)

AD1674–SPECIFICATIONS
AC SPECIFICATIONS
Parameter
Signal to Noise and Distortion (S/N+D) Ratio
Total Harmonic Distortion (THD)
Peak Spurious or Peak Harmonic Component
Full Power Bandwidth
Full Linear Bandwidth
Intermodulation Distortion (IMD)
SHA (Specifications are Included in Overall Timing Specifications)
DIGITAL SPECIFICATIONS
Parameter
LOGIC INPUTS
LOGIC OUTPUTS
NOTES
1
2
3
4
5
All min and max specifications are guaranteed.
Specifications subject to change without notice.
f
otherwise noted.
Specified at worst case temperatures and supplies after one minute warm-up.
See Figures 12 and 13 for other input frequencies and amplitudes.
See Figure 11.
fa = 9.08 kHz, fb = 9.58 kHz with f
IN
Second Order Products
Third Order Products
Aperture Delay
Aperture Jitter
Acquisition Time
V
V
I
I
C
V
V
I
C
IH
IL
OZ
amplitude = –0.5 dB (9.44 V p-p) 10 V bipolar mode unless otherwise noted. All measurements referred to –0 dB (9.997 V p-p) input signal unless
IH
IL
OH
OL
IN
OZ
High Level Input Voltage
Low Level Input Voltage
High Level Input Current (V
Low Level Input Current (V
Input Capacitance
High Level Output Voltage
Low Level Output Voltage
High-Z Leakage Current
High-Z Output Capacitance
SAMPLE
(T
–12 V
MIN
5
= 100 kHz. See Definition of Specifications section and Figure 15.
4
to T
(for all grades T
V
MAX
5%, f
EE
, with V
= –15 V
IN
IN
SAMPLE
= 0 V)
2, 3
= 5 V)
CC
= 100 kSPS, f
= +15 V
10% or –12 V
MIN
to T
MAX
Test Conditions
V
V
I
I
V
OH
OL
10% or +12 V
IN
IN
IN
, with V
IN
–4–
= 1.6 mA
= 0.5 mA
= 10 kHz, stand-alone mode unless otherwise noted)
= V
= 0 V
= 0 to V
Min
69
5%)
LOGIC
CC
= +15 V
AD1674J/A
LOGIC
Typ
70
–90
–92
1
500
–90
–90
50
250
1
5%, V
10% or +12 V
LOGIC
Max
0.008
–82
–80
–80
Min
+2.0
–0.5
–10
–10
+2.4
–10
–82
= +5 V
Min
70
1
500
10%, V
5%, V
AD1674K/B/T
Max
V
+0.8
+10
+10
10
+0.4
+10
10
LOGIC
LOGIC
EE
Typ
71
–90
–92
50
250
1
–90
–90
= –15 V
= +5 V
+0.5 V
1
Max
–82
0.008
–82
–80
–80
10% or
10%,
Units
V
V
pF
V
V
pF
A
A
A
REV. C
Units
dB
dB
%
dB
MHz
kHz
dB
dB
ns
ps
s