AD1674AR Analog Devices Inc, AD1674AR Datasheet - Page 5

• Manufacturer Part Number: AD1674AR
• Description: ADC Single SAR 100KSPS 12-Bit Parallel 28-Pin SOIC W
• Manufacturer: Analog Devices Inc

Specifications of AD1674AR

• Package: 28SOIC W
• Resolution: 12 Bit
• Sampling Rate: 100 KSPS
• Architecture: SAR
• Number Of Adcs: 1
• Number Of Analog Inputs: 2
• Digital Interface Type: Parallel
• Input Type: Voltage
• Polarity Of Input Voltage: Unipolar|Bipolar
• Rohs Status: RoHS non-compliant
• Number Of Bits: 12
• Sampling Rate (per Second): 100k
• Data Interface: Parallel
• Number Of Converters: 1
• Power Dissipation (max): 825mW
• Voltage Supply Source: Dual ±
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (0.300", 7.50mm Width)

REV. C
SWITCHING SPECIFICATIONS
CONVERTER START TIMING (Figure 1)
Parameter
Conversion Time
STS Delay from CE
CE Pulse Width
CS to CE Setup
CS Low During CE High t
R/C to CE Setup
R/C Low During CE High t
A
A
READ TIMING—FULL CONTROL MODE (Figure 2)
Parameter
Access Time
Data Valid After CE Low t
Output Float Delay
CS to CE Setup
R/C to CE Setup
A
CS Valid After CE Low
R/C High After CE Low t
A
NOTES
1
2
3
4
5
All min and max specifications are guaranteed.
Specifications subject to change without notice.
Test
Access Time High Z to Logic Low
Float Time Logic High to High Z
Access Time High Z to Logic High
Float Time Logic Low to High Z
t
required for an output to cross 0.4 V or 2.4 V.
0 C to T
At –40 C.
At –55 C.
t
loaded with the circuit of Figure 3.
0
0
0
0
DD
HL
8-Bit Cycle
12-Bit Cycle
to CE Setup
Valid During CE High t
to CE Setup
Valid After CE Low
is defined as the time required for the data lines to change 0.5 V when
is measured with the load circuit of Figure 3 and is defined as the time
MAX
.
Symbol Min Typ Max
t
t
t
t
t
t
t
Symbol Min Typ Max
t
t
t
t
t
t
t
DD
HD
HL
SSR
SRR
SAR
HSR
HRR
HAR
C
C
DSC
HEC
SSC
HSC
SRC
HRC
SAC
HAC
5
1
J, K, A, B, Grades
25
20
50
0
50
0
0
50
J, K, A, B, Grades
50
50
50
50
50
0
50
2
3
7
9
75
8
10
200
150
150
V
5 V
0 V
0 V
5 V
CP
(for all grades T
V
V
Min Typ Max Units
50
50
50
50
50
0
50
Min Typ Max Units
25
15
50
0
50
0
0
50
LOGIC
IH
2
4
T Grade
T Grade
= 2.4 V unless otherwise noted)
= +5 V
7
9
75
8
10
225 ns
150 ns
150 ns
C
100 pF
10 pF
100 pF
10 pF
OUT
10%, V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MIN
s
s
to T
–5–
MAX
EE
= –15 V
with V
DB11 – DB0
Figure 3. Load Circuit for Bus Timing Specifications
CC
STS
R/C
D
= +15 V
CE
__
CS
DB11 – DB0
A
OUT
_
0
10% or –12 V
IMPEDANCE
STS
R/C
Figure 1. Converter Start Timing
CE
CS
__
A
HIGH
_
0
C
OUT
10% or +12 V
Figure 2. Read Timing
t
SAC
t
SSR
t
SAR
t
SSC
t
5%; V
SRC
t
t
HRC
HSC
t
IL
t
t
SSR
DSC
DD
t
= 0.4 V,
t
HAC
HEC
5%,
t
I
I
HRR
OL
HIGH IMPEDANCE
OH
t
C
VALID
t
DATA
HS
t
t
t
HSR
HAR
HD
AD1674
t
HL
V
CP
HIGH
IMP.