ICS85357AG-01 IDT, Integrated Device Technology Inc, ICS85357AG-01 Datasheet - Page 6

• Manufacturer Part Number: ICS85357AG-01
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Multiplexerr

Specifications of ICS85357AG-01

• Number Of Clock Inputs: 4/2
• Mode Of Operation: Differential
• Output Frequency: 750MHz
• Output Logic Level: ECL/LVPECL
• Operating Supply Voltage (min): -3.135/3.135V
• Operating Supply Voltage (typ): -3.3/3.3V
• Operating Supply Voltage (max): -3.465/3.465V
• Package Type: TSSOP
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 20
• Lead Free Status / RoHS Status: Not Compliant

W
Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ V
generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock
swing is only 2.5V and V
T
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
85357AG-01
RTT =
ERMINATION FOR
IRING THE
((V
F
FOUT
OH
IGURE
+ V
D
OL
2A. LVPECL O
IFFERENTIAL
) / (V
1
CC
LVPECL O
Z
Z
– 2)) – 2
CC
o
o
= 50
= 50
= 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
I
F
Z
NPUT TO
o
IGURE
50
UTPUT
UTPUTS
1. S
T
A
D
RTT
ERMINATION
A
CLK_IN
50
IFFERENTIAL
PPLICATION
INGLE
CCEPT
0.1uF
V
C1
CC
FIN
- 2V
E
NDED
S
INGLE
www.idt.com
S
-
IGNAL
TO
R1
1K
V_REF
R2
1K
E
6
I
-3.3V LVPECL / ECL C
NDED
50 transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion. Figures 2A and 2B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
NFORMATION
D
V
RIVING
CC
+
-
L
FOUT
EVELS
F
D
IGURE
IFFERENTIAL
2B. LVPECL O
Z
Z
o
o
= 50
= 50
I
NPUT
125
84
ICS85357-01
UTPUT
LOCK
3.3V
125
84
T
ERMINATION
M
4:1
ULTIPLEXER
REV. B JULY 29, 2010
FIN
OR
CC
2:1
/2 is