ICS8533AGI-31 IDT, Integrated Device Technology Inc, ICS8533AGI-31 Datasheet

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ICS8533AGI-31

Manufacturer Part Number
ICS8533AGI-31
Description
Manufacturer
IDT, Integrated Device Technology Inc
Type
Clock Driverr
Datasheet

Specifications of ICS8533AGI-31

Number Of Clock Inputs
2
Mode Of Operation
Differential
Output Frequency
650MHz
Output Logic Level
LVPECL
Operating Supply Voltage (min)
3.135V
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.465V
Package Type
TSSOP
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
20
Lead Free Status / RoHS Status
Supplier Unconfirmed
LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Block Diagram
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification.
Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
General Description
differential clock or crystal inputs. The CLK, nCLK pair can accept
most standard differential input levels. The clock enable is
internally synchronized to eliminate runt pulses on the outputs
during asynchronous assertion/deassertion of the clock enable
pin.
Guaranteed output and part-to-part skew characteristics make the
ICS8533I-31 ideal for those applications demanding well defined
performance and repeatability.
IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER
XTAL_OUT
HiPerClockS™
ICS
XTAL_IN
CLK_SEL
CLK_EN
nCLK
CLK
The ICS8533I-31 is a low skew, high performance
1-to-4 Crystal Oscillator/Differential-to-3.3V
LVPECL Fanout Buffer and a member of the
HiPerClockS™ family of High Performance Clock
Solutions from IDT. The ICS8533I-31 has selectable
Pulludown
Pullup
Pulludown
Pullup
OSC
0
1
D
LE
Q
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
1
Features
Four differential LVPECL output pairs
Selectable differential CLK/nCLK or crystal oscillator interface
Maximum output frequency: 650MHz
Translates any single-ended input signal to 3.3V LVPECL levels
with resistor bias on nCLK input
Additive phase jitter, RMS: TBD
Output skew: 25ps (typical)
Part-to-part skew: 150ps (typical)
Propagation delay: 1.5ns (typical)
Full 3.3V supply mode
-40°C to 85°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
Pin Assignment
6.5mm x 4.4mm x 0.925mm
XTAL_OUT
ICS8533AGI-31 REV. A DECEMBER 13, 2007
CLK_SEL
XTAL_IN
CLK_EN
nCLK
20-Lead TSSOP
CLK
V
V
package body
nc
CC
EE
nc
ICS8533I-31
G Package
Top View
1
2
3
4
5
6
7
8
9
10
PRELIMINARY
20
19
18
17
16
15
14
13
12
11
ICS8533I-31
Q0
nQ0
V
Q1
nQ1
Q2
nQ2
Q3
nQ3
CC

Related parts for ICS8533AGI-31

ICS8533AGI-31 Summary of contents

Page 1

... Available in both standard (RoHS 5) and lead-free (RoHS 6) packages Q Q0 nQ0 Q1 nQ1 Q2 nQ2 Q3 nQ3 1 PRELIMINARY ICS8533I-31 Pin Assignment CLK_EN 2 19 nQ0 CLK_SEL CLK nCLK 5 16 nQ1 XTAL_IN XTAL_OUT 7 14 nQ2 nQ3 CC ICS8533I-31 20-Lead TSSOP 6.5mm x 4.4mm x 0.925mm package body G Package Top View ICS8533AGI-31 REV. A DECEMBER 13, 2007 ...

Page 2

... Differential clock output pair. LVPECL interface levels. Differential clock output pair. LVPECL interface levels. Differential clock output pair. LVPECL interface levels. Differential clock output pair. LVPECL interface levels. Test Conditions 2 PRELIMINARY Minimum Typical Maximum ICS8533AGI-31 REV. A DECEMBER 13, 2007 Units pF Ω k Ω k ...

Page 3

... Disabled; High Disabled; Low Disabled; High Enabled Enabled Enabled Enabled Enabled Input to Output Mode Differential to Differential Differential to Differential Single-ended to Differential Single-ended to Differential Single-ended to Differential Single-ended to Differential ICS8533AGI-31 REV. A DECEMBER 13, 2007 PRELIMINARY Polarity Non inverting Non inverting Non inverting Non inverting Inverting Inverting ...

Page 4

... Test Conditions Minimum 3.135 = 3.3V ± Test Conditions Minimum -0 3.465V 3.465V 3.465V -150 3.465V PRELIMINARY Typical Maximum 3.3 3.465 40 = -40°C to 85°C Typical Maximum 0.3 CC 0.8 5 150 ICS8533AGI-31 REV. A DECEMBER 13, 2007 Units V mA Units V V µA µA µA µA ...

Page 5

... Typical Maximum -150 - -40°C to 85°C A Minimum Typical Maximum V – 1 – 2 0.6 Minimum Typical Maximum Fundamental 14 ICS8533AGI-31 REV. A DECEMBER 13, 2007 PRELIMINARY Units 5 µA 150 µA µA µA 1.3 V – 0.85 V Units – 0.9 V – 1.7 V 1.0 V Units 25 MHz Ω ...

Page 6

... IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER = 3.3V ± -40°C to 85° Test Conditions ≤ ƒ 650MHz 650MHz, (Integration Range: 1.875MHz – 20MHz) 20% to 80% @ 50MHz 6 PRELIMINARY Minimum Typical Maximum 650 1.5 TBD 25 150 300 700 50 ICS8533AGI-31 REV. A DECEMBER 13, 2007 Units MHz ...

Page 7

... IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER V CC SCOPE nCLK Qx CLK nQx V EE Differential Input Level nCLK CLK nQ0:nQ3 Q0:Q3 Propagation Delay nQ0:nQ3 80% Q0: 20 Output Duty Cycle/Pulse Width/Period 7 PRELIMINARY V V Cross Points PERIOD t PW odc = x 100% t PERIOD ICS8533AGI-31 REV. A DECEMBER 13, 2007 CMR ...

Page 8

... All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated Single Ended Clock Input V_REF C1 0.1u Figure 2. Single-Ended Signal Driving Differential Input 8 PRELIMINARY CLK nCLK R2 1K ICS8533AGI-31 REV. A DECEMBER 13, 2007 ...

Page 9

... Zo = 50Ω LVDS Driven by a 3.3V LVDS Driver 2. 120 120 Zo = 60Ω 60Ω SSTL R1 R2 120 120 Driven by a 2.5V SSTL Driver ICS8533AGI-31 REV. A DECEMBER 13, 2007 PRELIMINARY 3.3V CLK nCLK HiPerClockS Input 3.3V CLK nCLK Receiver 3.3V CLK nCLK HiPerClockS ...

Page 10

... This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50Ω applications, R1 and R2 can be 100Ω. This can also be accomplished by removing R1 and making R2 50Ω 0.1µf XTAL_IN R2 XTAL_OUT 10 PRELIMINARY ICS8533AGI-31 REV. A DECEMBER 13, 2007 ...

Page 11

... FIN 50Ω RTT Figure 6B. 3.3V LVPECL Output Termination 11 3.3V 125Ω 125Ω 50Ω o FOUT Z = 50Ω o 84Ω 84Ω ICS8533AGI-31 REV. A DECEMBER 13, 2007 PRELIMINARY FIN ...

Page 12

... IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER = 3. 3.465V, which gives worst case results 3.465V * 40mA = 138.6mW EE_MAX * Pd_total + for 16 Lead TSSOP, Forced Convection θ vs. Air Flow JA 0 91.1°C/W 12 PRELIMINARY must be used. Assuming no air flow JA 1 2.5 86.7°C/W 84.6°C/W ICS8533AGI-31 REV. A DECEMBER 13, 2007 ...

Page 13

... IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER V OUT RL 50Ω CCO = V – 0.9V CC_MAX = V – 1.7V CC_MAX ] * (V – [(2V – CC_MAX OH_MAX ] * (V – [(2V – CC_MAX OL_MAX 13 – V ))/ – V CC_MAX OH_MAX L CC_MAX – V ))/ – V CC_MAX OL_MAX L] CC_MAX ICS8533AGI-31 REV. A DECEMBER 13, 2007 PRELIMINARY ) = OH_MAX ) = OL_MAX ...

Page 14

... All Dimensions in Millimeters Symbol Minimum 0.05 A2 0.80 b 0.19 c 0. 0.45 α 0° aaa Reference Document: JEDEC Publication 95, MO-153 14 ICS8533AGI-31 REV. A DECEMBER 13, 2007 PRELIMINARY 2.5 84.6°C/W Maximum 20 1.20 0.15 1.05 0.30 0.20 6.60 6.40 Basic 4.50 0.65 Basic 0.75 8° 0.10 ...

Page 15

... Lead TSSOP 20 Lead TSSOP “Lead-Free” 20 Lead TSSOP “Lead-Free” 20 Lead TSSOP 15 PRELIMINARY Shipping Packaging Temperature Tube -40°C to 85°C 2500 Tape & Reel -40°C to 85°C Tube -40°C to 85°C 2500 Tape & Reel -40°C to 85°C ICS8533AGI-31 REV. A DECEMBER 13, 2007 ...

Page 16

ICS8533I-31 LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/DIFFERENTIAL-TO- 3.3V LVPECL FANOUT BUFFER Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA ...

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