IDT5T9302PGI IDT, Integrated Device Technology Inc, IDT5T9302PGI Datasheet - Page 3

• Manufacturer Part Number: IDT5T9302PGI
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Driverr

Specifications of IDT5T9302PGI

• Number Of Clock Inputs: 2
• Mode Of Operation: Differential
• Output Frequency: 450MHz
• Output Logic Level: LVDS
• Operating Supply Voltage (min): 2.3V
• Operating Supply Voltage (typ): 2.5V
• Operating Supply Voltage (max): 2.7V
• Package Type: TSSOP
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 20
• Lead Free Status / RoHS Status: Not Compliant

Table 1. Pin Descriptions
NOTES:
1.
2.
3.
4.
Table 2. Pin Characteristics
NOTE: This parameter is measured at characterization but not tested.
IIDT™ LVDS CLOCK BUFFER TERABUFFER™ II
Symbol
C
IDT5T9302
2.5V LVDS 1:2 CLOCK BUFFER TERABUFFER™ II
IN
Inputs are capable of translating the following interface standards:
Single-ended 3.3V and 2.5V LVTTL levels
Differential HSTL and eHSTL levels
Differential LVEPECL (2.5V) and LVPECL (3.3V) levels
Differential LVDS levels
Differential CML levels
Because the gate controls are asynchronous, runt pulses are possible. It is the user's responsibility to either time the gate control
signals to minimize the possibility of runt pulses or be able to tolerate them in down stream circuitry.
It is recommended that the outputs be disabled before entering power-down mode. It is also recommended that the outputs remain
disabled until the device completes power-up after asserting PD.
The user must take precautions with any differential input interface standard being used in order to prevent instability when there is
no input signal.
Q{1:2}
Name
Q[1:2]
A[1:2]
A[1:2]
GND
SEL
V
PD
GL
nc
G
DD
Parameter
Input Capacitance
Output
Output
Input
Input
Input
Input
Input
Input
Adjustable
Adjustable
Type
LVTTL
LVTTL
LVTTL
LVTTL
Power
Power
LVDS
LVDS
(1, 4)
(1, 4)
(T
Description
Clock input. A
Complementary clock inputs. A[1:2] is the complementary side of A[1:2]
LVTTL single-ended operation, A[1:2] should be set to the desired toggle
voltage for A[1:2]:
3.3V LVTTL V
2.5V LVTTL V
Gate control for differential outputs Q1, Q1 and Q2, Q2. When G is LOW, the
differential outputs are active. When G is HIGH, the differential outputs are
asynchronously driven to the level designated by GL
Specifies output disable level. If HIGH, "true" outputs disable HIGH and
"complementary" outputs disable LOW. If LOW, "true" outputs disable LOW and
"complementary" outputs disable HIGH. See Table 3A.
Clock outputs.
Complementary clock outputs.
Reference clock select. When LOW, selects A2 and A2. When HIGH, selects A1
and A1. See Table 3B.
Power-down control. Shuts off entire chip. If LOW, the device goes into low
power mode. Inputs and outputs are disabled. Both "true" and “complementary”
outputs will pull to V
Power supply for the device core and inputs.
Power supply return for all power.
No connect; recommended to connect to GND.
A
= +25°C, F = 1.0MHz)
Test Conditions
[1:2]
REF
REF
is the "true" side of the differential clock input.
= 1650mV
= 1250mV
DD
3
. Set HIGH for normal operation.
)
Minimum
(2)
. See Table 3A.
Typical
(3)
IDT5T9302 REV. A APRIL 29, 2008
Maximum
PRELIMINARY
3
.
For
Units
pF