77V126L200TFI IDT, Integrated Device Technology Inc, 77V126L200TFI Datasheet - Page 10

• Manufacturer Part Number: 77V126L200TFI
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 77V126L200TFI

• Number Of Channels: 1
• Type Of Atm Phy Interface: UTOPIA
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Pin Count: 64
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

The Utopia signals are summarized below:
inputs to the 77V126. All Utopia signals are timed to these clocks.
available) to indicate that it has room in its transmit FIFO to accept at
least one 53-byte ATM cell. When the ATM layer device is ready to begin
passing the cell, it asserts TXEN (transmit enable) and TXSOC (start of
cell), coincident with the first byte of the cell on TXDATA. TXEN can
remain asserted for the duration of the cell transfer, or the ATM device
may deassert TXEN at any time once the cell transfer has begun; data is
transferred only when TXEN is asserted.
prepared to receive data. As with transmit, it may be asserted or deas-
serted at any time.
IDT77V126L200
Transmit and receive both utilize free running clocks, which are
In the transmit direction, the PHY first asserts TXCLAV (transmit cell
In the receive direction, RXEN indicates when the ATM device is
TXCLK
TXCLAV
TXEN
TXDATA[7:0],
TXPARITY
TXSOC
RXDATA[7:0]
RXPARITY
RXSOC
RXEN
RXCLAV
RXCLK
TXDATA[7:0]
TXPARITY
TXSOC
TXEN
TXCLAV
TXCLK
X
ATM to PHY
ATM to PHY
ATM to PHY
ATM to PHY
PHY to ATM
ATM to PHY
PHY to ATM
PHY to ATM
PHY to ATM
ATM to PHY
PHY to ATM
ATM to PHY
H1
Figure 4 Utopia Transmit Handshake - Single Cell
H2
P44
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in byte-mode as determined by bit 1 in the Master Control Register. In
cell-mode, which is the default, the 77V126L200 does not assert
TXCLAV until it has enough room in it's transmit FIFO to accept a
complete cell, and doesn't assert RXCLAV until it has a complete cell in
the receive FIFO. It will not deassert TXCLAV or RXCLAV until at or near
the end of the transfer of a cell.
complete cell. It will modulate TXCLAV to prevent the FIFO from over-
flowing. Likewise, it may assert RXCLAV before a complete cell has
been received, and will modulate RXCLAV to prevent the FIFO from
underflowing. There is generally little advantage to the byte-mode, so
most users will leave the 77V126L200 in the default cell-mode.
asserted for one clock, coincident with the first byte of each cell. Odd
parity is utilized across each 8-bit data field, which means that for an all-
zero pattern. the corresponding parity bit is one.
shake.
P45
Note that this Utopia interface can be operated in either cell-mode or
In byte-mode, the phy can assert TXCLAV before it has room for a
In both transmit and receive, TXSOC and RXSOC (start of cell) is
The following figures show examples of the Utopia Level 1 hand-
P46
P47
P48
X
December 2004
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