IDT77V106L25TFI IDT, Integrated Device Technology Inc, IDT77V106L25TFI Datasheet - Page 20
![](/photos/31/27/312736/64pin_tqfp_sml.jpg)
IDT77V106L25TFI
Manufacturer Part Number
IDT77V106L25TFI
Description
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet
1.IDT77V106L25TFI.pdf
(27 pages)
Specifications of IDT77V106L25TFI
Data Rate
25.6/51.2Mbps
Number Of Channels
1
Type Of Atm Phy Interface
UTOPIA
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Pin Count
64
Mounting
Surface Mount
Lead Free Status / RoHS Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IDT77V106L25TFI
Manufacturer:
NEC
Quantity:
4 102
Part Number:
IDT77V106L25TFI
Manufacturer:
IDT
Quantity:
20 000
LED DRIVER AND HEC STATUS/CONTROL REGISTER
Address: 0x03
LOW BYTE COUNTER REGISTER [7:0]
Address: 0x04
HIGH BYTE COUNTER REGISTER [15:8]
Address: 0x05
COUNTER SELECT REGISTER
Address: 0x06
Note:
[7:0]
[7:0]
4, 3
IDT77V106L25
Bit
Bit
Bit
Bit
7
6
5
2
1
0
7
6
5
4
3
2
1
0
For proper operation, only one bit may be set in the Counter Selected Register at any time.
Type
Type
Type
Type
R/W
R/W
R/W
—
—
—
—
R
R
R
R
R
R
W
W
W
W
Initial State
Initial State
Initial State
Initial State
00 = 1 cycle
0 = enable
0 = enable
& Replace
1 = empty
Checking
Calculate
0x00
0x00
0
1
1
0
0
0
0
0
0
0
0
Reserved
Disable Receive HEC Checking (HEC Enable)
When not set, the HEC is calculated on first 4 bytes of received cell, and compared against the 5th byte. When set
(= 1), the HEC byte is not checked.
Disable Transmit HEC Calculate & Replace
the first four replace bytes of that cell.
RxREF Pulse Width Select
Bit #4 3
Transmit FIFO Status 1 = TxFIFO empty
TxLED Status 0 = Cell Transmitted 1 = Cell Not Transmitted
RxLED Status 0 = Cell Received
Provides low-byte of counter value selected via the Counter Select Register.
Provides high-byte of counter value selected via the Counter Select Register.
Reserved
Reserved
Reserved
Reserved
Symbol Error Counter
Tx Cell Counter
Rx Cell Counter Does not count HEC errored cells. Even when bit 6 of the Master Control Register is Cleared.
Receive Hec Error Counter
When set, the 5th header byte of cells queued for transmit is not replaced with the HEC calculated across
0 0 RxREF active for 1 cycle of the recovered clock
0 1 RxREF active for 2 cycle of the recovered clock
1 0 RxREF active for 4 cycle of the recovered clock
1 1 RxREF active for 8 cycle of the recovered clock
20
1 = Cell Not Received
Function
Function
Function
Function
0 = TxFIFO not empty